Memory device and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJe-Min Hung, Win-San Khwa, Meng-Fan Chang
Life of this patent
Estimating the term…
Abstract
An Input/Output (I/O) circuit for a memory device is provided. The I/O circuit includes a charge integration circuit coupled to a bitline of the memory device. The charge integration circuit provides a sensing voltage based on a decrease of a voltage on the bitline. A comparator is coupled to the charge integration circuit. The comparator compares the sensing voltage with a reference voltage and provides an output voltage based on the comparison. A time-to-digital converter coupled to the comparator. The time-to-digital convertor converts a time associated with the output voltage to a digital value.
Claims20
An Input/Output (I/O) circuit for a memory device, wherein the I/O circuit comprises:
- a charge integration circuit coupled to a bitline of the memory device, wherein the charge integration circuit provides a sensing voltage based on a decrease of a voltage on the bitline;
- a comparator coupled to the charge integration circuit, wherein the comparator compares the sensing voltage with a reference voltage and provides an output voltage based on the comparison;
- and
- a time-to-digital converter coupled to the comparator, wherein the time-to-digital convertor converts a time associated with the output voltage to a digital value.
A memory device comprising:
- a memory array comprising a plurality of rows and a plurality of columns, wherein each of the plurality of columns comprises a first plurality of memory cells connected to a bit line of a plurality of bitlines;
- a plurality of multiplexers, each of the plurality of multiplexers associated with a predetermined number of bitlines of the plurality of bitlines;
- and
- a plurality of Input/Output (I/O) circuits, wherein each of the plurality of I/O circuits is associated with one of the plurality of multiplexers, wherein a multiplexer connects an I/O circuit associated with the multiplexer to a bitline of the predetermined number of bitlines, and wherein the I/O circuit senses multiply-accumulate value for the bitline in time domain.
A method of Multiply-Accumulate (MAC) operation in a memory device, the method comprising:
- connecting a charge integration circuit to a bitline of the memory device;
- charging, by the charge integration circuit, a sensing node based on a decrease of a voltage on the bitline;
- comparing, by a comparator coupled to the charge integration circuit, a sensing voltage of the sensing node with a reference voltage;
- providing, by the comparator, an output voltage based on the comparison;
- and
- converting, by a time-to-digital converter coupled to the comparator, a time associated with the output voltage to a MAC value.
Dependencies are inferred from the claim text.