Integrated circuit with dummy boundary cells

An integrated circuit (IC), comprising:

• a plurality of first macros, each comprising a first macro boundary and a first main pattern surrounded by the first macro boundary, wherein the first macro boundary comprises a plurality of first dummy boundary cells and the first main pattern comprises a plurality of transistors with a first gate length;
• a plurality of second macros, each comprising a second macro boundary and a second main pattern surrounded by the second macro boundary, wherein the second macro boundary comprises a plurality of second dummy boundary cells and the second main pattern comprises a plurality of transistors with a second gate length, and the first gate length is different from the second gate length;
• and
• a top channel arranged between the first and second macros, and comprising the first dummy boundary cells,
• wherein a plurality of dummy patterns of the first dummy boundary cells have the first gate length, and a plurality of dummy patterns of the second dummy boundary cells have the second gate length.

An integrated circuit (IC), comprising:

• at least one first macro comprising a first macro boundary and a first main pattern surrounded by the first macro boundary, wherein the first macro boundary is formed by a plurality of first dummy boundary cells;
• at least one second macro comprising a second macro boundary and a second main pattern surrounded by the second macro boundary, wherein the second macro boundary is formed by a plurality of second dummy boundary cells;
• and
• a top channel between the first and second macros, wherein the top channel is filled with the first dummy boundary cells,
• wherein a first gate length of dummy patterns within the first dummy boundary cells is greater than a second gate length of dummy patterns within the second dummy boundary cells.