System for a decision feedback equalizer
AssigneeCeremorphic, Inc.
InventorsAjay Mantha, Poorna Chandrika Kondeti
Life of this patent
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Abstract
A decision feedback equalizer includes a summer, a slicer, and a feedback circuit. The summer is configured to receive an input signal and a correction signal from the feedback circuit and generate a summer output signal. The slicer includes a first slicer and a second slicer, both are configured to receive the summer output signal as an input, and output a slicer output signal. The feedback circuit is configured to receive the slicer output signal, and based on the slicer output signal, generate the correction signal. The input signal is received at a first clock rate. The first slicer and the second slicer sample the input signal at a second clock rate, about half the first clock rate.
Claims19
A decision feedback equalizer, comprising:
- a summer;
- a slicer including a first slicer and a second slicer;
- and
- a feedback circuit,
- wherein the summer is configured to receive an input signal and a correction signal from the feedback circuit to generate a summer output signal,
- wherein the first slicer and the second slicer are configured to receive the summer output signal as an input, sample the received input, and output a slicer output signal,
- wherein the feedback circuit is configured to receive the slicer output signal, and based on the slicer output signal, generate the correction signal,
- wherein the input signal is received at a first clock rate,
- wherein the first slicer and the second slicer sample the received input at a second clock rate approximately half the first clock rate, and
- wherein, the summer includes an input inverter based transconductor configured to receive the input signal and a unity inverter based load, wherein an input of the unity inverter based load is coupled to an output of the input inverter based transconductor, and wherein the correction signal from the feedback circuit is coupled to an output of the unity inverter based load.
A decision feedback equalizer, comprising:
- a summer;
- a slicer including a first slicer and a second slicer;
- and
- a feedback circuit,
- wherein the summer is configured to receive an input signal and a correction signal from the feedback circuit to generate a summer output signal,
- wherein the first slicer and the second slicer are configured to receive the summer output signal as an input, sample the received input, and output a slicer output signal,
- wherein the feedback circuit is configured to receive the slicer output signal, and based on the slicer output signal, generate the correction signal,
- wherein the input signal is received at a first clock rate,
- wherein the first slicer and the second slicer sample the received input at a second clock rate approximately half the first clock rate, and
- wherein, each of the first slicer and the second slicer includes an input circuit, a reset circuit, and a regeneration circuit, wherein, the input circuit is active during a track phase, the regeneration circuit is active during a regeneration phase, and the reset circuit is active during a reset phase.
A decision feedback equalizer, comprising:
- a summer;
- a slicer including a first slicer and a second slicer;
- and
- a feedback circuit,
- wherein the summer is configured to receive an input signal and a correction signal from the feedback circuit to generate a summer output signal,
- wherein the first slicer and the second slicer are configured to receive the summer output signal as an input, sample the received input, and output a slicer output signal,
- wherein the feedback circuit is configured to receive the slicer output signal, and based on the slicer output signal, generate the correction signal,
- wherein the input signal is received at a first clock rate,
- wherein the first slicer and the second slicer sample the received input at a second clock rate approximately half the first clock rate, and
- wherein the feedback circuit includes a plurality of DFE taps, each of the plurality of decision feedback equalizer (DFE) taps configured to receive a DFE tap correction signal, a polarity of the DFE tap correction signal is determined by the slicer output signal, and a plurality of DFE tap correction signals from the plurality of DFE taps are collectively fed as the correction signal to the summer.
Dependencies are inferred from the claim text.