Programmable gain low noise amplifier

An amplifier circuit, comprising:

• an input node for receiving an input signal;
• a gain stage, having an input and an output;
• a digital step attenuation circuit, having an input and an output coupled to the input of the gain stage, and adapted to apply a selected attenuation to a signal received at the input node;
• an input capacitor having a first terminal coupled to the input of the digital step attenuation circuit and a second terminal coupled to an output of the digital step attenuation circuit to receive a voltage corresponding to an opposite polarity voltage corresponding to the received signal as attenuated by the digital step attenuation circuit;
• control logic adapted to control the digital step attenuation circuit to apply a selected attenuation to a received signal at the input of the digital step attenuation circuit;
• and
• a variable output resistor, coupled between the output of the gain stage and a ground level;
• wherein the control logic is further adapted to control the variable output resistor to select an output gain of the gain stage.

An analog front end, comprising:

• an analog-to-digital converter;
• a digital downsampler, having an input coupled to an output of the analog to digital converter, and having in-phase and quadrature phase outputs;
• an amplifier circuit, comprising:
• first and second input terminals for receiving positive and negative input signals, respectively;
• first and second gain stages, each having an input and an output, the outputs of the first and second gain stages coupled to inputs of the analog-to-digital converter;
• a first digital step attenuation circuit, having an input coupled to the first input terminal and an output coupled to the input of the first gain stage;
• a second digital step attenuation circuit, having an input coupled to the second input terminal and an output coupled to the second input of the first gain stage;
• a first input capacitor, coupled between the first input terminal and an output of the second digital step attenuation circuit;
• and
• a second input capacitor, coupled between the second input terminal and an output of the first digital step attenuation circuit;
• and
• control logic adapted to control the first and second digital step attenuation circuits to apply a selected attenuation to a received signal at their respective inputs;
• wherein each of the first and second digital step attenuation circuits comprises:
• a digitally controllable series capacitance;
• and
• a digitally controllable shunt capacitance;
• and
• and wherein the control logic is further adapted to control the digitally controllable series capacitance and the digitally controllable shunt capacitance.