US 11,935,617 B2 · Non-destructive pattern identification at a memory device

Abstract

Methods, systems, and devices for non-destructive pattern identification at a memory device are described. A memory device may perform pattern identification within the memory device and output a flag indicating whether a first data pattern matches with a second data pattern. The memory device may access one or more memory cells, via a word line, and latch the second data pattern of the memory cells to a sense amplifier. The memory device may deactivate the word line, which may result in isolating the memory cells from potential destruction of data. The memory device may write a first data pattern to the sense amplifier and compare the first data pattern and second data pattern at the sense amplifier. The memory device may output a signal indicating whether the data patterns match.

Claims20

Dependent claims

A method, comprising:

receiving, at a memory device, signaling that indicates a first data pattern and one or more addresses of memory cells within the memory device;
latching a second data pattern associated with the one or more addresses by one or more sense amplifiers based at least in part on receiving the signaling;
writing, by the memory device, the first data pattern to the one or more sense amplifiers after latching the second data pattern by the one or more sense amplifiers;
and
outputting, by the memory device, an indication of whether the first data pattern matches the second data pattern based at least in part on writing the first data pattern to the one or more sense amplifiers, wherein the indication of whether the first data pattern matches the second data pattern is based at least in part on whether a current associated with writing the first data pattern to the one or more sense amplifiers satisfies a threshold.

2 more elements

An apparatus, comprising:

an array of memory cells, the array comprising a set of word lines and a set of digit lines;
one or more sense amplifiers operable to couple with the set of digit lines;
a data line operable to couple with the one or more sense amplifiers;
circuitry operable to generate a current based at least in part on a mismatch between first data written to the one or more sense amplifiers from the data line and second data latched by the one or more sense amplifiers;
and
a controller operable to cause the apparatus to:
latch the second data to the one or more sense amplifiers based at least in part on activating one or more word lines of the set of word lines;
deactivate the one or more word lines after latching the second data to the one or more sense amplifiers;
write the first data to the one or more sense amplifiers via the data line after deactivating the one or more word lines;
and
output an indication of whether the first data matches the second data based at least in part on writing the first data to the one or more sense amplifiers.

8 more elements

An apparatus, comprising:

a memory array;
and
a controller operable to cause the apparatus to:
receive signaling that indicates a first data pattern and one or more addresses of memory cells within the memory array;
latch a second data pattern associated with the one or more addresses by one or more sense amplifiers based at least in part on receiving the signaling;
write the first data pattern to the one or more sense amplifiers after latching the second data pattern by the one or more sense amplifiers;
and
output an indication of whether the first data pattern matches the second data pattern based at least in part on writing the first data pattern to the one or more sense amplifiers, wherein the indication of whether the first data pattern matches the second data pattern is based at least in part on whether a current associated with writing the first data pattern to the one or more sense amplifiers satisfies a threshold.

5 more elements

Dependencies are inferred from the claim text.

Non-destructive pattern identification at a memory device

Life of this patent

Non-destructive pattern identification at a memory device

Life of this patent

Abstract

Claims20