Memory device having hidden refresh

An integrated circuit (IC) memory device comprising:

• an array of storage cells configured into multiple banks;
• interface circuitry to receive refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode;
• on-die refresh control circuitry to selectively generate local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode;
• mode register circuitry to store a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode;
• wherein the on-die refresh control circuitry is configured to conditionally transmit a corrective action control signal during operation in the second refresh mode;
• for the first refresh mode, a first timing interval between an Activate command and a corresponding memory access command is of a first duration;
• for the second refresh mode, a second timing interval between the Activate command and the corresponding memory access command is of a second duration longer than the first duration;
• and
• wherein the designated hidden refresh interval is based on the second timing interval.

A method of operation in a memory device, the method comprising:

• storing data in an array of storage cells organized into multiple banks;
• configuring the memory device to generate hidden refresh commands on-die during a hidden refresh mode of operation;
• receiving commands from a host memory controller to start a memory access operation with at least one selected bank from the multiple banks, the memory access operation occurring during a memory access interval;
• performing a hidden refresh operation to at least one idle bank of the multiple banks during a designated hidden refresh interval that at least partially overlaps the memory access interval;
• and
• generating a corrective action control signal indicating a request for the host memory controller due to a failed operation caused by a collision between a memory request command to a given bank of the multiple banks and a hidden refresh operation to the given bank.

A method of operation in a memory device, the method comprising:

• storing data in an array of storage cells organized into multiple banks;
• configuring the memory device to generate hidden refresh commands on-die during a hidden refresh mode of operation;
• receiving commands from a host memory controller to start a memory access operation with at least one selected bank from the multiple banks, the memory access operation occurring during a memory access interval;
• performing a hidden refresh operation to at least one idle bank of the multiple banks during a designated hidden refresh interval that at least partially overlaps the memory access interval;
• notifying the host memory controller of any corrective action following the performing of the hidden refresh operation;
• for a non-hidden refresh mode, a first timing interval between an Activate command and a corresponding memory access command is of a first duration;
• for the hidden refresh mode, a second timing interval between the Activate command and the corresponding memory access command is of a second duration longer than the first duration;
• and
• wherein the designated hidden refresh interval is based on the second timing interval.

An integrated circuit (IC) dynamic random access memory (DRAM) device, comprising:

• mode register circuitry to store a refresh mode control value;
• on-die refresh control circuitry selectively enabled based on the mode control value;
• a first bank of storage cells responsive to a first memory access request from a host memory controller to perform a first memory access operation during a memory access interval;
• a second bank of storage cells responsive to hidden refresh commands generated on-die by the refresh control circuitry to undergo a hidden refresh operation during a designated hidden refresh interval that at least partially overlaps the memory access interval;
• and
• wherein the refresh control circuitry conditionally dispatches a corrective action control signal to the host memory controller indicating a retry request for the host memory controller due to a failed operation caused by a collision between a memory request command to a given bank of the multiple banks and a hidden refresh operation to the given bank.