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US 11,931,856 B2Granted
Polishing pad, process for preparing the same, and process for preparing a semiconductor device using the same
AssigneeSK enpulse Co., Ltd.
InventorsSunghoon Yun, Hye Young Heo, Jang Won Seo
Life of this patent
Estimating the term…
Abstract
Embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, a process for preparing the same, and a process for preparing a semiconductor device using the same. In the polishing pad according to the embodiment, the size (or diameter) and distribution of a plurality of pores are adjusted, whereby the polishing performance such as polishing rate and within-wafer non-uniformity can be further enhanced.
Claims6
A polishing pad, which comprises a polishing layer comprising a plurality of pores,
- wherein, in a diameter distribution of the plurality of pores, a number average diameter (Da) of the plurality of pores, defined as an average value obtained by dividing a sum of diameters of the plurality of pores by a number of the pores, ranges from 15 μm to 50 μm, and
- an area ratio, defined as a percentage of an area (Au) of pores having a diameter at least 200% greater than the number average diameter of the plurality of pores to a total area of the polishing surface ranges from 0.9% to less than 12%,
- wherein a diameter (Du) of pores having the diameter at least 200% greater than the number average diameter of the plurality of pores is 100 μm or more.
Dependencies are inferred from the claim text.