Methods and apparatuses for temperature independent delay circuitry

9An apparatus comprising:

• a memory comprising timing circuitry comprising a first circuit component having impedance that is proportional to absolute temperature (PTAT) and a second circuit component having impedance that is complementary to absolute temperature (CTAT), wherein the timing chain circuitry is a row address strobe (RAS) timing chain circuitry, the RAS timing chain circuitry comprising a command decoder circuit, an address decoder circuit, a row decoder circuit, memory array circuitry, or any combination thereof.

An apparatus comprising:

• a memory comprising timing circuitry comprising a first circuit component having impedance that is proportional to absolute temperature (PTAT) and a second circuit component having impedance that is complementary to absolute temperature (CTAT), wherein the first circuit component is a different type of circuit component than the second circuit component.

An apparatus comprising:

• a memory comprising timing circuitry comprising a first circuit component having impedance that is proportional to absolute temperature (PTAT) and a second circuit component having impedance that is complementary to absolute temperature (CTAT), and
• a third circuit component having impedance that is proportional to absolute temperature (PTAT), wherein the first circuit component, the second circuit component, and the third circuit component share a common node.

A delay circuit comprising:

• a first circuit component coupled to a first transistor and an output node, and having impedance that is proportional to absolute temperature (PTAT);
• and
• a second circuit component coupled to the first transistor and the output node, and further coupled in parallel with at least a first element of the first circuit component, wherein the second circuit component has an impedance that is complementary to absolute temperature (CTAT), and wherein the first circuit component is configured to provide an output signal at the output node.