Multilevel semiconductor device and structure with image sensors and wafer bonding
AssigneeMonolithic 3D Inc.
InventorsZvi Or-Bach, Deepak C. Sekar, Brian Cronquist
Life of this patent
Estimating the term…
Abstract
An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level with an oxide to oxide bond; a plurality of pixel control circuits; a plurality of memory circuits; and a third level disposed underneath the first level, where the third level includes a plurality of third transistors.
Claims20
An integrated device, the device comprising:
- a first level comprising a first mono-crystal layer, said first mono-crystal layer comprising a plurality of single crystal transistors;
- an overlying oxide disposed on top of said first level;
- a second level comprising a second mono-crystal layer, said second level overlaying said oxide,
- wherein said second mono-crystal layer comprises a plurality of image sensors,
- wherein said second level is bonded to said first level with an oxide to oxide bond;
- a plurality of pixel control circuits;
- a plurality of memory circuits;
- and
- a third level disposed underneath said first level,
- wherein said third level comprises a plurality of third transistors.
An integrated device, the device comprising:
- a first level comprising a first mono-crystal layer, said first mono-crystal layer comprising a plurality of single crystal transistors;
- an overlying oxide disposed on top of said first level;
- a second level comprising a second mono-crystal layer, said second level overlaying said oxide,
- wherein said second mono-crystal layer comprises a plurality of image sensors,
- wherein said plurality of image sensors are aligned to said plurality of single crystal transistors with a less than 400 nm alignment error,
- wherein said second level is bonded to said first level with an oxide to oxide bond;
- and
- a plurality of memory circuits.
An integrated device, the device comprising:
- a first level comprising a first mono-crystal layer, said first mono-crystal layer comprising a plurality of single crystal transistors;
- an overlying oxide disposed on top of said first level;
- a second level comprising a second mono-crystal layer, said second level overlaying said oxide;
- a plurality of through layer vias,
- wherein a diameter said plurality of through layer vias is less than 400 nm,
- wherein said second mono-crystal layer comprises a plurality of image sensors,
- wherein said second level is bonded to said first level with an oxide to oxide bond;
- and
- a plurality of memory circuits.
Dependencies are inferred from the claim text.