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US 11,928,056 B2Granted
Memory controller for allocating cache lines and method of operating the same
AssigneeSK hynix Inc.
InventorDo Hun Kim
Life of this patent
Estimating the term…
Abstract
The present technology relates to an electronic device. A memory controller that increases a hit ratio of a cache memory includes a memory buffer configured to store command data corresponding to a request received from a host, and a cache memory configured to cache the command data. The cache memory stores the command data by allocating cache lines based on a component that outputs the command data and a flag included in the command data.
Claims12
A memory controller comprising:
- a memory buffer configured to store command data corresponding to a request received from a host;
- and
- a cache memory configured to cache the command data,
- wherein the cache memory divides the command data and allocates divided command data to cache lines, based on reference addresses of the memory buffer and a flag, the flag being included in the command data and including a start address and an end address of a storage region in the memory buffer in which the command data is stored, and
- wherein when the start address is an address other than the reference addresses, the cache memory:
- obtains first divided command data corresponding to a first interval between the start address and a first reference address, which is a next address of the start address, among the reference addresses, the first divided command data being a first part of the command data, and
- obtains second divided command data corresponding to a second interval between the first reference address and a second reference address, which is a next address of the first reference address, among the reference addresses, the second divided command data being a second part of the command data.
4 more elements
A method of operating a memory controller including a memory buffer and a cache memory, the method comprising:
- storing command data corresponding to a request received from a host in the memory buffer;
- and
- caching the command data in the cache memory,
- wherein the caching comprises dividing the command data and allocating divided command data to cache lines, based on reference addresses of the memory buffer and a flag, the flag being included in the command data and including a start address and an end address of a storage region in the memory buffer in which the command data is stored, and
- wherein the allocating of the divided command data to the cache lines comprises:
- obtaining, in response to the start address that is an address other than the reference addresses, first divided command data corresponding to a first interval between the start address and a first reference address, which is a next address of the start address, among the reference addresses, the first divided command data being a first part of the command data;
- and
- obtaining second divided command data corresponding to a second interval between the first reference address and a second reference address, which is a next address of the first reference address, among the reference addresses, the second divided command data being a second part of the command data.
5 more elements
Dependencies are inferred from the claim text.