Introduction and detection of parity error in a UART

A microcontroller, comprising:

• a universal asynchronous receiver/transmitter (UART), a transmission register to include information capable to be transmitted by the UART to one or more first destinations outside of the UART;
• a receive register to include information capable to be received by the UART from one or more second destinations outside of the UART;
• a virtual remappable pin;
• a parity error check circuit to evaluate contents of the receive register for a parity error;
• and
• a control logic to:
• determine contents of the transmission register, the contents to include underlying data and a parity bit based on the underlying data;
• route the contents of the transmission register through the virtual remappable pin to the receive register;
• before reception of the entire contents of the transmission register at the receive register, cause modified contents to be provided to the receive register, the modified contents to cause a parity error, the modified contents to include different underlying data or a different parity bit than the contents of the transmission register;
• and
• determine whether the parity error check circuit detected the parity error.

A method, comprising, in a universal asynchronous receiver/transmitter (UART):

• determining contents of a transmission register, the transmission register to include information capable to be transmitted by the UART to one or more first destinations outside of the UART, the contents to include underlying data and a parity bit based on the underlying data;
• routing the contents of the transmission register through a virtual remappable pin to a receive register capable of receiving information from one or more second destinations outside of the UART;
• before reception of the entire contents of the transmission register at the receive register, causing modified contents to be provided to the receive register, the modified contents including different underlying data or a different parity bit than the contents of the transmission register, the modified contents to cause a parity error;
• and
• determining whether a parity error check circuit detected a parity error in the receive register.