US 11,925,025 B2Granted

Semiconductor device and method of controlling the same

AssigneeRenesas Electronics Corporation

InventorJunichi Suzuki

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Abstract

An occupied area of the switch circuit electrically connected to a memory cell is reduced to reduce the size of a semiconductor device. A semiconductor device according to an embodiment includes a memory cell on a semiconductor substrate and a semiconductor chip in which a switch circuit electrically connected to the memory cell is formed, wherein the switch circuit includes a second transistor electrically connected to the memory cell, and the second transistor includes a second word gate formed on the semiconductor substrate through a third gate insulating film, and a second coupling gate formed on the semiconductor substrate through a fourth gate insulating film having a thickness greater than that of the third gate insulating film, wherein a voltage higher than a voltage applied to the second word gate is applied to the second coupling gate of the second transistor when a current is applied to the memory cell.

Claims8

Dependent claims

A semiconductor device comprising a memory cell and a switch circuit formed on a semiconductor substrate,

wherein the switch circuit is disposed outside the memory cell and electrically connected to the memory cell,
wherein the memory cell includes a plurality of transistors including a first transistor,
wherein the switch circuit comprises a second transistor electrically connected to the first transistor,
wherein the second transistor includes:
a first word gate formed on a first gate insulating film;
a second word gate formed on a second gate insulating film having a thickness thicker than the first gate insulating film,
wherein in the second transistor, when a current flows through the switch circuit, a first voltage is supplied from the outside of the switch circuit, so that a first region of the semiconductor substrate under the first word gate becomes conductive state,
wherein in the second transistor, when a current flows through the switch circuit, a second voltage is supplied from the outside of the switch circuit, so that a second region of the semiconductor substrate under the first coupling gate becomes conductive state, and
wherein the second voltage is higher than the first voltage.

6 more elements

A semiconductor device comprising a memory cell and a switch circuit formed on a semiconductor substrate,

wherein the switch circuit is disposed outside the memory cell and electrically connected to the memory cell,
wherein the memory cell includes a plurality of transistors including a first transistor,
wherein the switch circuit comprises a second transistor electrically connected to the first transistor,
wherein the first transistor includes:
a first word gate formed on a first gate insulating film;
and
a second word gate formed on a second gate insulating film having a thickness thicker than the first gate insulating film,
wherein the second transistor includes:
a second word gate formed on a third gate insulating film;
and
a second coupling gate formed on a fourth gate insulating film having a thickness thicker than the third gate insulating film,
wherein the first transistor includes a first source electrode electrically connected to a second source electrode of the second transistor, and
wherein the semiconductor device further comprises:
a first driver circuit configured to supply a first voltage with the first word gate;
a second driver circuit configured to supply a second voltage with the second word gate;
a third driver circuit configured to supply a third voltage higher than the first voltage with the first coupling gate;
and
a fourth driver circuit configured to supply a fourth voltage higher than the second voltage with the second coupling gate.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/095,018Filed 11 Nov 2020
Priority: JP 2019-20440212 Nov 2019
Published: US 2021/0143168 A113 May 2021
Granted: 5 Mar 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10B 43/30
EEPROM devices comprising charge-trapping gate insulators: characterised by the memory core region
H10D 30/6892
Characterised by the shapes, relative sizes or dispositions of the floating gate electrode: having at least one additional gate other than the…
G11C 16/26
Auxiliary circuits, e.g. for writing into memory: sensing or reading circuits; Data output circuits
H10B 10/18
Static random access memory [SRAM] devices: peripheral circuit regions