Frequency divider for non-overlapping clock signals
AssigneeQUALCOMM Incorporated
InventorNagarjuna Nallam
Life of this patent
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Abstract
A frequency divider is provided that includes a plurality of latches for dividing an input clock according to an integer frequency divisor N of three or greater. Each latch is coupled to a corresponding pair of logic gates. For each latch, one of the logic gates in the corresponding pair controls a setting of the latch whereas a remaining one of the logic gates in the corresponding pair controls a resetting of the latch. Each latch outputs a pair of overlapping clock signals that are divided in frequency with respect to the input clock and have a 50% duty cycle. Each logic gate processes a pair of the overlapping clock signal and the input clock signal to provide a non-overlapping clock signal of the same frequency of the overlapping clock signals but have a (50/N) % duty cycle.
Claims26
A frequency divider, comprising:
- a plurality of stages arranged in series from a first stage to an Nth stage, wherein N is an integer of three or greater and each stage comprises:
- a 3-input logic gate having an output terminal coupled to a first input terminal of a 2-input logic gate, and
- wherein an output terminal of the 2-input logic gate in each preceding stage in the series is coupled to a first input terminal of the 3-input logic gate in a subsequent stage in the series, and wherein an output terminal of the 2-input logic gate in the Nth stage is coupled to a first input terminal of the 3-input logic gate in the first stage.
A frequency divider, comprising:
- a differential clock source configured to output a positive input clock signal and a negative input clock signal that is a complement of the positive input clock signal;
- a plurality of N latches, wherein N is a plural positive integer greater than two;
- a plurality of N first logic gates, each first logic gate having a first output terminal coupled to a reset input terminal of a corresponding one of the latches, each first logic gate being configured to process a unique pair of overlapping clock signals from a plurality of 2N overlapping clock signals with one of the positive input clock signal and the negative input clock signal to output, at the first output terminal, a corresponding non-overlapping clock signal from a first plurality of N non-overlapping clock signals;
- and
- a plurality of N second logic gates, each second logic gate having a second output terminal coupled to a set input terminal of a corresponding one of the latches, each second logic gate being configured to process a unique pair of overlapping clock signals from the plurality of 2N overlapping clock signals with one of the positive input clock signal and the negative input clock signal to output, at the second output terminal, a corresponding non-overlapping clock signal from a second plurality of N non-overlapping clock signals.
A divide-by-N frequency divider, comprising:
- a differential clock source configured to cycle a positive input clock signal and a negative input clock signal at a first frequency, wherein the negative input clock signal is a complement of the positive input clock signal;
- a plurality of N latches, each latch being configured to output a corresponding pair of overlapping clock signals from 2N overlapping clock signals that cycle at a second frequency that is 1/Nth of the first frequency and have approximately a 50% duty cycle, wherein N is an integer of 3 or greater;
- and
- a plurality of 2N logic gates configured to output 2N non-overlapping clock signals that cycle at the second frequency and have approximately a (50/N) % duty cycle, each logic gate being configured to process two of the 2N overlapping clock signals with one of the negative input clock signal and the positive input clock signal to output a corresponding one of the 2N non-overlapping clock signals at an output terminal of the logic gate.
A method of frequency division, comprising:
- dividing an input clock signal in frequency by a divisor N into a plurality of 2N overlapping clock signals;
- wherein N is an integer of three or greater and each overlapping clock signal has a duty cycle of approximately 50%;
- and
- processing pairs of the overlapping clock signals with the input clock signal to divide the input clock signal in frequency by the divisor N into a plurality of 2N non-overlapping clock signals each having a duty cycle of approximately (50/N) %.
Dependencies are inferred from the claim text.