Low power operational amplifier trim offset circuitry

A circuit comprising:

• a reference circuit comprising a set of reference voltage nodes and comprising one or more bandgap reference elements;
• a sample and hold circuit coupled to the reference circuit, the sample and hold circuit comprising a first node, a second node, a first storage element, a second storage element, a first buffer, and a second buffer, the first node coupled to a first reference voltage node of the reference voltage nodes, to the first storage element, and to the first buffer, the second node coupled to a second reference voltage node of the reference voltage nodes, to the second storage element, and to the second buffer;
• a digital-to-analog conversion (DAC) circuit coupled to the sample and hold circuit and comprising a plurality of transistor pairs, wherein a first transistor of each transistor pair is coupled to the first buffer, wherein a second transistor of each transistor pair is coupled to the second buffer, wherein transistors of each transistor pair are coupled together;
• and
• drain switching elements coupled to drain terminals of the first and second transistors of each transistor pair.

An operational amplifier trim circuit comprising:

• a first storage element;
• a second storage element;
• a plurality of transistor pairs, wherein each of the plurality of transistor pairs includes a first transistor that includes a first gate coupled to the first storage element and a second transistor that includes a second gate coupled to the second storage element;
• and
• pairs of switching elements coupled to drain terminals of transistors among the transistor pairs and configured to selectively couple one or more portions of a trim current to an operational amplifier in accordance with a control code.