Device disaggregation for improved performance
AssigneeAdeia Semiconductor Inc.
InventorsJavier A. Delacruz, Don Draper, Jung Ko, Steven L. Teig
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Abstract
The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.
Claims32
A method of manufacturing a programmable logic device from disaggregated device components, the method comprising:
- forming one or more routing layers on a wafer;
- and
- hybrid bonding one or more dies comprising logic components to the wafer to form, via the one or more routing layers, a plurality of routing paths communicatively coupling at least some of the logic components of the one or more dies to one another to form the programmable logic device.
A method of manufacturing a microelectronic component, the method comprising:
- providing one or more dies comprising active circuitry fabricated in a first process node, the active circuitry comprising a plurality of circuit elements among the one or more dies;
- providing a wafer comprising one or more routing layers fabricated in a second process node, the first process node being a more advanced node than the second process node;
- and
- direct hybrid bonding the one or more dies to the wafer to interconnect the one or more routing layers with the active circuitry, wherein at least some of the one or more routing layers communicatively couple at least some of the plurality of circuit elements to one another.
Dependencies are inferred from the claim text.