Memory-based distributed processor architecture

A method performed for operating a distributed memory device comprising:

• compiling, by a compiler, a task for the distributed memory device, the task requiring at least one computation, the compiling comprising:
• determining a number of words that are required simultaneously to perform the task, and
• providing instructions for writing words that need to be accessed simultaneously in a plurality of memory banks disposed on a substrate of a chip when a number of words that can be accessed simultaneously from one of the plurality of memory banks is lower than the number of words that are required simultaneously;
• receiving, by a configuration manager disposed on the substrate of the chip, an indication to perform the task;
• and
• in response to receiving the indication, configuring a memory controller disposed in the substrate of the chip to:
• within a first line access cycle:
• access at least one first word from a first memory bank from the plurality of memory banks using a first memory line,
• send the at least one first word to at least one processing unit disposed on the substrate of the chip and connected to the memory controller, and
• open a first memory line in a second memory bank to access a second address from the second memory bank from the plurality of memory banks, and
• within a second line access cycle:
• access at least one second word from the second memory bank using the first memory line,
• send the at least one second word to at least one processing unit disposed on the substrate of the chip and connected to the memory controller, and
• access a third address from the first memory bank using a second memory line in the first memory bank.