# US 11,910,734 B2 · Phase change memory cell with ovonic threshold switch

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- Number: US 11,910,734 B2
- Document ID: US11910734B2
- Status: Granted
- Kind: B2
- Application number: 18/311,922
- Filed: 2023-05-04
- Published: 2023-09-28
- Granted: 2024-02-20
- Earliest claimed: 2020-12-11
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Nanbo Gong; Takashi Ando; Robert L. Bruce; Alexander Reznicek; Bahman Hekmatshoartabari
- Web page: https://patentgrep.com/patent/US11910734B2

## CPC

- H10B 63/24: {of the Ovonic threshold switching type}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/066: {by filling of openings, e.g. damascene method}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8265: {on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices}
- H10N 70/841: {Electrodes}
- H10N 70/882: {Compounds of sulfur, selenium or tellurium, e.g. chalcogenides}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.

## Claims

### Claim 1

A method comprising:
forming a bottom electrode on a substrate;
forming a phase change material layer on the bottom electrode;
forming an ovonic threshold switching layer above the phase change material layer, wherein vertical sidewalls of the bottom electrode and the phase change material layer are aligned with one another; and
forming a first buffer layer above the ovonic threshold switching layer, wherein a width of the first buffer layer is greater than a width of the ovonic threshold switching layer.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising:
forming a top electrode above the first buffer layer, the first buffer layer physically separating the ovonic threshold switching layer and the top electrode, wherein
a width of the ovonic threshold switching layer is less than a width of the top electrode.

### Claim 3 (depends on 2)

The method according to claim 2, wherein
a width of the phase change material layer is less than the width of the top electrode.

### Claim 4 (depends on 1)

The method according to claim 1, further comprising:
forming a dielectric surrounding the bottom electrode, the phase change material layer, and the ovonic threshold switching layer, wherein a portion of the first buffer layer covers an upper horizontal portion of the dielectric.

### Claim 5 (depends on 1)

The method according to claim 1, further comprising:
forming a second buffer layer, the second buffer layer physically separating the ovonic threshold switching layer and the phase change material layer.

### Claim 6 (depends on 1)

The method according to claim 1, further comprising:
forming an array of structures, wherein the structures are wired together forming word lines and bit lines.

### Claim 7

A method comprising:
forming a bottom electrode on a substrate;
forming a phase change material layer on the bottom electrode;
forming a first buffer layer on the phase change material layer;
forming an ovonic threshold switching layer above the first buffer layer, wherein vertical sidewalls of the bottom electrode, the phase change material layer and the ovonic threshold switching layer are aligned with one another; and
forming a second buffer layer above the ovonic threshold switching layer, wherein a width of the second buffer layer is greater than a width of the ovonic threshold switching layer.

### Claim 8 (depends on 1)

The method according to claim 1, further comprising:
forming a top electrode above the second buffer layer, the second buffer layer physically separating the ovonic threshold switching layer and the top electrode.

### Claim 9 (depends on 8)

The method according to claim 8, wherein
a width of the ovonic threshold switching layer is less than a width of the top electrode.

### Claim 10 (depends on 2)

The method according to claim 2, wherein
a width of the phase change material layer is less than the width of the top electrode.

### Claim 11 (depends on 7)

The method according to claim 7, further comprising:
forming a dielectric surrounding the bottom electrode, the phase change material layer, and the ovonic threshold switching layer.

### Claim 12 (depends on 7)

The method according to claim 7, wherein a portion of the second buffer layer covers an upper horizontal portion of the dielectric.

### Claim 13 (depends on 7)

The method according to claim 7, further comprising:
forming an array of structures, wherein the structures are wired together forming word lines and bit lines.

### Claim 14

A method comprising:
forming a bottom electrode on a substrate;
forming a phase change material layer on the bottom electrode;
forming a first buffer layer on the phase change material layer;
forming an ovonic threshold switching layer above the first buffer layer, wherein vertical sidewalls of the bottom electrode, the phase change material layer and the ovonic threshold switching layer are aligned with one another; and
forming a second buffer layer above the ovonic threshold switching layer, wherein a width of the second buffer layer is greater than a width of the ovonic threshold switching layer,
wherein the second buffer layer covers an upper horizontal portion of a first dielectric surrounding the phase change material layer, the first buffer layer and the ovonic threshold switching layer.

### Claim 15 (depends on 14)

The method according to claim 14, further comprising:
forming a top electrode above the second buffer layer, the second buffer layer physically separating the ovonic threshold switching layer and the top electrode.

### Claim 16 (depends on 15)

The method according to claim 15, wherein
a width of the ovonic threshold switching layer is less than a width of the top electrode.

### Claim 17 (depends on 16)

The method according to claim 16, wherein
a width of the phase change material layer is less than the width of the top electrode.

### Claim 18 (depends on 14)

The method according to claim 14, further comprising:
forming a dielectric surrounding the bottom electrode, the phase change material layer, and the ovonic threshold switching layer.

### Claim 19 (depends on 18)

The method according to claim 18, wherein a portion of the second buffer layer covers an upper horizontal portion of the dielectric.

### Claim 20 (depends on 14)

The method according to claim 14, further comprising:
forming an array of structures, wherein the structures are wired together forming word lines and bit lines.