# US 11,910,732 B2 · Resistive memory devices using a carbon-based conductor line and methods for forming the same

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- Number: US 11,910,732 B2
- Document ID: US11910732B2
- Status: Granted
- Kind: B2
- Application number: 17/750,484
- Filed: 2022-05-23
- Published: 2022-09-08
- Granted: 2024-02-20
- Earliest claimed: 2019-12-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Hung-Li Chiang; Chao-Ching Cheng; Tzu-Chiang Chen; Lain-Jong Li
- Web page: https://patentgrep.com/patent/US11910732B2

## CPC

- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10B 63/24: {of the Ovonic threshold switching type}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/066: {by filling of openings, e.g. damascene method}
- H10N 70/8265: {on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices}
- H10N 70/8845: {Carbon or carbides}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 2213/72: Array wherein the access device being a diode
- G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate.

## Claims

### Claim 1

A method of forming at least one resistive memory array over a substrate, wherein each of the at least one resistive memory array is formed by:
forming an array of rail structures that extend along a first horizontal direction over the substrate, wherein each of the rail structures comprises a respective lower bit line and a respective upper bit line;
forming dielectric isolation structures extending along a second horizontal direction over the array of rail structures, wherein sidewalls of the rail structures are physically exposed to line trenches located between neighboring pairs of the dielectric isolation structures;
forming a layer stack of a resistive memory material layer and a selector material layer within each of the line trenches; and
forming a word line on each of the layer stacks within unfilled volumes of the line trenches, wherein:
lower bit lines comprise a first material selected from a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement and a conductive material other than the carbon-based conductive material; and
the upper bit lines comprise a second material that is different from the first material and selected from the carbon-based conductive material and the conductive material other than the carbon-based conductive material.

### Claim 2 (depends on 1)

The method of claim 1, wherein the carbon-based conductive material is selected from carbon nanotubes and graphene in sheets or nanoribbons.

### Claim 3 (depends on 1)

The method of claim 1, wherein each of the resistive memory material layer and the selector material layer is formed by a conformal deposition process as a respective continuous material layer extending continuously over each rail structure within the array of rail structures and into each of the line trenches.

### Claim 4 (depends on 1)

The method of claim 1, wherein each rail structure within the array of rail structures comprises a respective inter-bit-line dielectric rail located between the respective lower bit line and the respective upper bit line.

### Claim 5 (depends on 1)

The method of claim 1, wherein the at least one resistive memory array comprises a plurality of resistive memory arrays that are sequentially formed at different levels of metal interconnect structures over the substrate.

### Claim 6

A method of forming a resistive memory device, comprising:
forming an array of rail structures that extend along a first horizontal direction over a substrate, wherein each of the rail structures comprises at least one bit line;
forming a layer stack of a resistive memory material layer and a selector material layer over the array of rail structures; and
forming word lines that laterally extend along a second horizontal direction and are laterally spaced apart along the first horizontal direction over the layer stack, wherein each of the word lines includes a respective horizontally-extending portion that overlie the rail structures and a respective row of downward-protruding portions that protrude downward from the respective horizontally-extending portion,
wherein:
the word lines or at least a subset of the bit lines comprise a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement;
each rail structure within the array of rail structures comprises a vertical stack including a respective lower bit line, a respective inter-bit-line dielectric rail, and a respective upper bit line;
wherein one of the respective lower bit line and the respective upper bit line comprises the carbon-based conductive material; and
wherein another of the respective lower bit line and the respective upper bit line comprises a conductive material other than the carbon-based conductive material.

### Claim 7 (depends on 6)

The method of claim 6, wherein the carbon-based conductive material is selected from carbon nanotubes and graphene in sheets or nanoribbons.

### Claim 8 (depends on 6)

The method of claim 6, wherein each layer stack continuously extends over each rail structure within the array of rail structures and contacts sidewalls of each bit line within the array of rail structures.

### Claim 9 (depends on 6)

The method of claim 6, wherein:
each resistive memory material layer comprises a material selected from a phase change memory material and a vacancy-modulated conductive oxide material; and
each selector material layer comprises a material selected from an ovonic threshold switch material and a p-n junction diode material.

### Claim 10 (depends on 6)

The method of claim 6, wherein each of the word lines include a respective carbon-based conductive material rail that comprises the carbon-based conductive material containing the hybridized carbon atoms in the hexagonal arrangement.

### Claim 11 (depends on 10)

The method of claim 10, wherein each of the word lines include a respective metallic nitride liner comprising first horizontally-extending portions contacting first segments of a bottom surface of the respective carbon-based conductive material rail, vertically-extending portions contacting sidewalls of the layer stack, and second horizontally-extending portions contacting top surfaces of horizontally-extending portions of the layer stack.

### Claim 12 (depends on 6)

The method of claim 6, wherein each rail structure within the array of rail structures comprises a pair of straight sidewalls that laterally extends along the first horizontal direction and vertically extends from a topmost surface of a respective rail structure to a bottommost surface of the respective rail structure.

### Claim 13 (depends on 6)

The method of claim 6, further comprising:
forming first bit line contact structures comprising at least one metallic material on a respective one of the lower bit lines; and
forming second bit line contact structures comprising the at least one metallic material on a respective one of the upper bit lines.

### Claim 14 (depends on 6)

The method of claim 6, wherein:
the horizontally-extending portion of each word line comprises the carbon-based conductive material; and
the downward-protruding portions of each word line comprise at least one metallic material.

### Claim 15 (depends on 6)

The method of claim 6, further comprising forming dielectric isolation structures, wherein the dielectric isolation structures include a respective horizontally-extending portion that overlie the rail structures and a respective row of downward-protruding portions that protrude downward between neighboring pairs of the rail structures.

### Claim 16

A method of forming a memory device, comprising:
forming vertical stacks of a respective lower bit line, a respective inter-bit-line dielectric rail, and a respective upper bit line;
forming a layer stack of a resistive memory material layer and a selector material layer over sidewall of the vertical stacks; and
forming word lines that laterally extend along a horizontal direction that is perpendicular to a lengthwise direction of the vertical stacks, wherein each of the word lines includes a respective horizontally-extending portion that overlie each of the vertical stacks and a respective row of downward-protruding portions that protrude downward from the respective horizontally-extending portion between neighboring pairs of the vertical stacks,
wherein:
at least one set selected from a set of the word lines, a set of the lower bit lines, and a set of the upper bit lines comprises a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement;
the lower bit lines comprise a first material selected from the carbon-based conductive material and a conductive material other than the carbon-based conductive material; and
the upper bit lines comprise a second material that is different from the first material and selected from the carbon-based conductive material and the conductive material other than the carbon-based conductive material.

### Claim 17 (depends on 16)

The method of claim 16, wherein the carbon-based conductive material is selected from carbon nanotubes and graphene in sheets or nanoribbons.

### Claim 18 (depends on 16)

The method of claim 16, further comprising forming dielectric isolation structures including a respective horizontally-extending portion that overlie the rail structures and a respective row of downward-protruding portions that protrude downward between neighboring pairs of the vertical stacks, wherein the word lines and the dielectric isolation structures form a laterally alternating sequence that alternate along the first horizontal direction, and have top surfaces that are located within a horizontal plane.

### Claim 19 (depends on 16)

The method of claim 16, wherein each segment of the resistive memory material layers located between a neighboring pair of a word line selected from the word lines and a bit line selected from the lower bit lines and the upper bit lines constitutes a resistive memory element.

### Claim 20 (depends on 16)

The method of claim 16, wherein the at least one resistive memory array comprises a plurality of resistive memory arrays located at different levels and overlie, or underlie, each other or one another.