# US 11,910,723 B2 · Memory device with electrically parallel source lines

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- Number: US 11,910,723 B2
- Document ID: US11910723B2
- Status: Granted
- Kind: B2
- Application number: 17/032,638
- Filed: 2020-09-25
- Published: 2021-05-06
- Granted: 2024-02-20
- Earliest claimed: 2019-10-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ku-Feng Lin
- Web page: https://patentgrep.com/patent/US11910723B2

## CPC

- G11C 11/2253: {Address circuits or decoders}
- H10N 50/80: Constructional details
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 11/1653: {Address circuits or decoders}
- G11C 11/1655: {Bit-line or column circuits}
- G11C 11/1657: {Word-line or row circuits}
- G11C 11/1659: {Cell access}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/2259: {Cell access}
- G11C 11/2273: {Reading or sensing circuits or methods}
- G11C 13/0023: {Address circuits or decoders}
- G11C 13/003: {Cell access}
- G11C 13/004: {Reading or sensing circuits or methods}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/01: Manufacture or treatment
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 8/14: Word line organisation; Word line lay-out
- G11C 2213/82: Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line. Each memory cell includes: a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line. The memory device further includes a word-line driver and a bit-line driver. A first number of the source lines are connected in parallel.

## Claims

### Claim 1

A memory device, comprising:
a memory cell array having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line, wherein each memory cell comprises:
a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and
a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line;
a word-line driver coupled to the word line and configured to generate the word line signal;
a bit-line driver coupled to the bit line and configured to generate the bit line signal; and
wherein corresponding source lines for the each column of memory cells are electrically connected in parallel through one or more metal contacts that extend perpendicular to the source lines.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the bit line is a first metal track and the source line is a second metal track.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the second metal track is below the first metal track.

### Claim 4 (depends on 2)

The memory device of claim 2, wherein the first metal track has a first sheet resistance and the second metal track has a second sheet resistance, and a first number of the source lines is determined based on the first sheet resistance and the second sheet resistance.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the first number of the source lines is determined to be the greatest integer less than or equal to a ratio of the second sheet resistance to the first sheet resistance.

### Claim 6 (depends on 2)

The memory device of claim 2, wherein a first number of the source lines are connected in parallel through a third metal contact track below the first number of source lines.

### Claim 7 (depends on 2)

The memory device of claim 2, wherein a first number of the source lines are connected in parallel through a third metal track above the first number of source lines.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein a first number of the source lines are in columns adjacent to each other.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein a first number of the source lines are in columns not all adjacent to each other.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the storage device is a magnetic tunnel junction (MTJ), the first resistance state is a high resistance state, and the second resistance state is a low resistance state.

### Claim 11 (depends on 1)

The memory device of claim 1, wherein the selection device is a transistor with a gate coupled to the word line.

### Claim 12

A memory cell, comprising:
a storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal; and
a transistor connected in series with the storage device, the transistor being configured to provide access to the storage device in response to a word line signal at a gate of the transistor; and
a plurality of source lines connected to the transistor, wherein corresponding source lines for the each column of memory cells are electrically connected in parallel through one or more metal contacts that extend perpendicular to the source lines.

### Claim 13 (depends on 12)

The memory cell of claim 12, further comprising:
a bit line coupled to the storage device, wherein the bit line comprises a first metal track; and
wherein the plurality of source lines comprises a plurality of second metal tracks connected in parallel.

### Claim 14 (depends on 13)

The memory cell of claim 13, wherein the first metal track has a first sheet resistance and the second metal track has a second sheet resistance, the plurality of source lines comprise a first number of source lines determined based on the first sheet resistance and the second sheet resistance.

### Claim 15 (depends on 12)

The memory cell of claim 12, wherein the plurality of source lines are connected in parallel by a metal contact track below the plurality of source lines.

### Claim 16 (depends on 12)

The memory cell of claim 12, wherein the plurality of source lines are connected in parallel by a third metal track above the plurality of source lines.

### Claim 17

A method, comprising:
providing a memory cell array having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line, wherein each memory cell comprises:
a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and
a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line;
coupling a word-line driver to the word line to generate the word line signal;
coupling a bit-line driver the bit line to generate the bit line signal; and
electrically connecting corresponding source lines for the each column of memory cells in parallel through one or more metal contacts that extend perpendicular to the source lines.

### Claim 18 (depends on 17)

The method of claim 17, wherein the bit line is a first metal track and the source line is a second metal track, wherein the first metal track has a first sheet resistance and the second metal track has a second sheet resistance, and wherein the method further comprises:
determining a first number of the source lines based on the first sheet resistance and the second sheet resistance.

### Claim 19 (depends on 17)

The method of claim 17, wherein the one or more metal contacts are below the corresponding source lines.

### Claim 20 (depends on 17)

The method of claim 17, wherein the one or more metal contacts are above the corresponding source lines.