# US 11,910,722 B2 · Subtractive top via as a bottom electrode contact for an embedded memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,910,722 B2 - Document ID: US11910722B2 - Status: Granted - Kind: B2 - Application number: 17/542,696 - Filed: 2021-12-06 - Published: 2023-06-08 - Granted: 2024-02-20 - Earliest claimed: 2021-12-06 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Ashim Dutta; Chih-Chao Yang - Web page: https://patentgrep.com/patent/US11910722B2 ## CPC - H10N 50/01: Manufacture or treatment - G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell} - H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices - H10N 50/10: Magnetoresistive devices - H10N 50/80: Constructional details - H10N 50/85: Materials of the active region - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Embodiments of the invention include a subtractive top via as a bottom electrode contact for an embedded memory structure. Forming the bottom electrode contact includes depositing a conductive material on an underlayer and etching the conductive material to form an extended via and a conductive pad as an integral unit. The extended via extends from the conductive pad such that the extended via is adjacent to a memory structure, the extended via being formed as a first contact for the memory structure. ## Claims ### Claim 1 A method comprising: depositing a conductive material on an underlayer; and etching the conductive material to form both an extended via elongated in a first dimension and a conductive pad elongated in a second dimension perpendicular to the first dimension as an integral unit, the extended via extending from the conductive pad such that the extended via is adjacent to a memory structure, the extended via being formed as a first contact for the memory structure, wherein the conductive material is patterned into a plurality of portions in preparation for the etching of the conductive material to form the extended via and the conductive pad from one of the plurality of portions. ### Claim 2 (depends on 1) The method of claim 1, wherein a lithography mask is used as a pattern to etch the conductive material into the extended via and the conductive pad. ### Claim 3 (depends on 1) The method of claim 1, wherein an interlayer dielectric material is formed on the extended via and the conductive pad, such that the memory structure is positioned on the extended via and a portion of the interlayer dielectric material. ### Claim 4 (depends on 1) The method of claim 1, wherein a width of a top portion of the extended via is smaller than a width of a bottom portion of the extended via and a width of the memory structure. ### Claim 5 (depends on 1) The method of claim 1, wherein the memory structure comprises a stack of memory layers configured to store data, the stack of memory layers having been patterned to be positioned adjacent to the extended via. ### Claim 6 (depends on 1) The method of claim 1, wherein the etching forms another one of the plurality of portions into a metal line. ### Claim 7 (depends on 1) The method of claim 1, wherein an encapsulation material is formed on sides of the memory structure and a second contact is formed on the memory structure. ### Claim 8 (depends on 1) The method of claim 1, wherein anisotropic etching is used to from the extended via and the conductive pad as the integral unit. ### Claim 9 (depends on 1) The method of claim 1, wherein the conductive material comprises a noble metal. ### Claim 10 (depends on 1) The method of claim 1, wherein the conductive material excludes copper. ### Claim 11 (depends on 1) The method of claim 1, wherein a periphery of the integral unit excludes a liner material. ### Claim 12 A structure comprising: an integral unit comprising an extended via and a conductive pad, the integral unit having been formed of a single conductive material so as to have no seam between the extended via and the conductive pad, the extended via extending from the conductive pad; and a memory structure adjacent to the extended via, a contact being formed adjacent to the memory structure opposite the extended via. ### Claim 13 (depends on 12) The structure of claim 12, wherein an interlayer dielectric material is formed on the extended via and the conductive pad, such that the memory structure is positioned on the extended via and a portion of the interlayer dielectric material. ### Claim 14 (depends on 12) The structure of claim 12, wherein a width of a top portion of the extended via is smaller than a width of a bottom portion of the extended via and a width of the memory structure. ### Claim 15 (depends on 12) The structure of claim 12, wherein the memory structure comprises a stack of memory layers configured to store data. ### Claim 16 (depends on 12) The structure of claim 12, wherein an encapsulation material is formed on sides of the memory structure and a second contact is formed on the memory structure. ### Claim 17 (depends on 12) The structure of claim 12, wherein a periphery of the integral unit excludes a liner material. ### Claim 18 A method of forming a structure, the method comprising: forming an integral unit comprising an extended via and a conductive pad, the integral unit having been formed of a single conductive material so as to have no seam between the extended via and the conductive pad, the extended via extending from the conductive pad; and forming a memory structure adjacent to the extended via, a contact being formed adjacent to the memory structure opposite the extended via. ### Claim 19 (depends on 18) The method of claim 18, wherein: a width of a top portion of the extended via is smaller than a width of a bottom portion of the extended via and a width of the memory structure; a periphery of the integral unit excludes a liner material; and the extended via being formed as a bottom contact for the memory structure.