# US 11,910,679 B2 · Method of manufacturing display panel with circuit-layer stack including metal, oxide, and capping layers, and display panel manufactured by the same

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- Number: US 11,910,679 B2
- Document ID: US11910679B2
- Status: Granted
- Kind: B2
- Application number: 18/121,646
- Filed: 2023-03-15
- Published: 2023-07-20
- Granted: 2024-02-20
- Earliest claimed: 2020-01-17
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Gyungmin Baek; Juhyun Lee; Hongsick Park; Hyuneok Shin
- Web page: https://patentgrep.com/patent/US11910679B2

## CPC

- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- H10K 59/1201: {Manufacture or treatment}
- H10K 59/1213: {the pixel elements being TFTs}
- H10K 59/8791: {Arrangements for improving contrast, e.g. preventing reflection of ambient light}
- H10K 71/621: {Providing a shape to conductive layers, e.g. patterning or selective deposition}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A method of manufacturing a display panel includes forming a circuit layer including a gate, a source, and a drain on a base substrate and forming a light emitting element layer on the circuit layer. The forming of the circuit layer includes sequentially forming a preliminary metal layer, a preliminary oxide layer comprising molybdenum and tantalum, and a preliminary capping layer which comprise a preliminary electrode layer, cleaning the preliminary electrode layer, forming a photoresist layer pattern on the preliminary electrode layer, etching the preliminary electrode layer, and removing the photoresist layer pattern. During the etching of the preliminary electrode layer, a ratio between a removal speed ER1 of the preliminary oxide layer and a removal speed ER2 of the preliminary metal layer satisfies Equation 1 to maintain a low reflection property 1≤ER2/ER1≤3. [Equation 1]

## Claims

### Claim 1

A display panel comprising:
a base substrate;
a circuit layer disposed on the base substrate and comprising a gate, a source, and a drain; and
a light emitting element layer disposed on the circuit layer,
wherein at least one of the gate, the source, and the drain comprises:
a metal layer;
an oxide layer disposed on the metal layer and comprising molybdenum and tantalum; and
a capping layer disposed on the oxide layer and comprising at least one compound selected from AZO, GZO, ITZO IZO, ZIO, and ZTO.

### Claim 2 (depends on 1)

The display panel of claim 1, wherein a content ratio of the molybdenum and the tantalum in the oxide layer is in a range of about 94:6 at % to about 98:2 at %.

### Claim 3 (depends on 1)

The display panel of claim 1, wherein the oxide layer comprises MoO2 and TaO.

### Claim 4 (depends on 1)

The display panel of claim 1, wherein the capping layer has a mean reflectivity of about 20% or less in a wavelength region in a range of about 400 nm to about 800 nm.

### Claim 5 (depends on 1)

The display panel of claim 1, wherein the capping layer has a thickness in a range of about 100 Å to about 1000 Å.

### Claim 6 (depends on 1)

The display panel of claim 1, wherein the capping layer has a transmittance of about 90% or more in a wavelength region in a range of about 400 nm to about 800 nm.

### Claim 7 (depends on 1)

The display panel of claim 1, wherein the at least one compound selected from AZO, GZO, ITZO, IZO, ZIO, and ZTO is an amorphous conductive metal oxide.

### Claim 8 (depends on 1)

The display panel of claim 1, wherein the oxide layer has a thickness in a range of about 100 Å to 1500 Å.

### Claim 9 (depends on 1)

The display panel of claim 1, wherein the metal layer comprises:
a single layer including at least one compound selected from Cu or Al; or
multilayers comprising Cu/Ti, Al/Ti, or Ti/Al/Ti.