# US 11,910,675 B2 · Display device

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- Number: US 11,910,675 B2
- Document ID: US11910675B2
- Status: Granted
- Kind: B2
- Application number: 17/811,976
- Filed: 2022-07-12
- Published: 2022-11-17
- Granted: 2024-02-20
- Earliest claimed: 2020-02-07
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Yoonjong Cho; Donghwi Kim; Jin Jeon
- Web page: https://patentgrep.com/patent/US11910675B2

## CPC

- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- H10D 30/6743: {Silicon}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 50/80: Constructional details
- H10K 50/88: Terminals, e.g. bond pads
- H10K 59/1213: {the pixel elements being TFTs}
- H10K 59/1315: {comprising structures specially adapted for lowering the resistance}
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A display device includes a first thin-film transistor (TFT) including a first semiconductor layer including silicon semiconductor and a first gate electrode insulated from the first semiconductor layer, a first interlayer insulating layer covering the first gate electrode, a second TFT arranged on the first interlayer insulating layer and including a second semiconductor layer including oxide semiconductor and a second gate electrode insulated from the second semiconductor layer, a second interlayer insulating layer covering the second gate electrode, a first power supply voltage line arranged on the second interlayer insulating layer, a first planarization layer covering the first power supply voltage line, and a data line arranged on the first planarization layer and at least partially overlapping the first power supply voltage line.

## Claims

### Claim 1

A display device comprising:
a first transistor;
a second transistor connected to a data line and the first transistor;
a third transistor connected to a node and the first transistor;
a fourth transistor connected to the node and a first initialization voltage line;
a fifth transistor connected to a power supply voltage line and the first transistor;
a sixth transistor connected to the first transistor and a light emitting device;
a seventh transistor connected to the light emitting device and a second initialization voltage line; and
a first capacitor connected to a driving voltage line and the node,
wherein each of the first to the seventh transistors comprises a semiconductor layer and a gate electrode, the semiconductor layer comprising a source region, a drain region and a channel region overlapped with the gate electrode,
wherein the gate electrode of the first transistor is connected to the node,
wherein each of the semiconductor layer of the third transistor and the semiconductor layer of the fourth transistor comprises oxide semiconductor, and
wherein the power supply voltage line overlaps the channel region of the semiconductor layer of the third transistor and the channel region of the semiconductor layer of the fourth transistor.

### Claim 2 (depends on 1)

The display device of claim 1, wherein the first capacitor comprises a first electrode and a second electrode, the first capacitor overlapping the channel region of the semiconductor layer of the first transistor.

### Claim 3 (depends on 2)

The display device of claim 2, wherein a part of the first electrode of the first capacitor is the gate electrode of the first transistor, and
wherein the second electrode of the first capacitor and the gate electrode of the third transistor are arranged on a same layer.

### Claim 4 (depends on 2)

The display device of claim 2, wherein the second electrode of the first capacitor is electrically connected to the power supply voltage line.

### Claim 5 (depends on 1)

The display device of claim 1, wherein the first capacitor is arranged on a layer between the semiconductor layer of the first transistor and the semiconductor layer of the third transistor.

### Claim 6 (depends on 1)

The display device of claim 1, further comprising a node connection line electrically connected to the gate electrode of the first transistor and the semiconductor layer of the fourth transistor.

### Claim 7 (depends on 1)

The display device of claim 1, further comprising a second capacitor connected to the gate electrode of the second transistor and the gate electrode of the first transistor.

### Claim 8 (depends on 7)

The display device of claim 7, wherein the power supply voltage line overlaps the second capacitor.

### Claim 9 (depends on 7)

The display device of claim 7, wherein the second capacitor comprises a third electrode and a fourth electrode,
wherein the third electrode of the second capacitor and the gate electrode of the first transistor are arranged on a same layer, and
wherein the fourth electrode of the second capacitor and the semiconductor layer of the third transistor are arranged on a same layer.

### Claim 10 (depends on 9)

The display device of claim 9, wherein the fourth electrode of the second capacitor comprises oxide semiconductor.

### Claim 11 (depends on 10)

The display device of claim 10, wherein the fourth electrode of the second capacitor is an extended part from the semiconductor layer of the third transistor.

### Claim 12 (depends on 1)

The display device of claim 1, further comprising:
a first scan line overlapping the channel region of the semiconductor layer of the second transistor;
a second scan line overlapping the channel region of the semiconductor layer of the third transistor;
a third scan line overlapping the channel region of the semiconductor layer of the fourth transistor;
a fourth scan line overlapping the channel region of the semiconductor layer of the seventh transistor; and
a control line overlapping the channel regions of the semiconductor layer of the fifth transistor and the semiconductor layer of the sixth transistor.

### Claim 13 (depends on 12)

The display device of claim 12, wherein the control line and the first scan line are arranged on a same layer, and the first scan line and the second scan line are arranged on different layers from each other.

### Claim 14 (depends on 12)

The display device of claim 12, wherein the third scan line comprises a lower scan line and an upper scan line arranged on different layers.

### Claim 15 (depends on 12)

The display device of claim 12, wherein the fourth scan line comprises a lower scan line and an upper scan line arranged on different layers.

### Claim 16 (depends on 1)

The display device of claim 1, wherein the power supply voltage line overlaps a part of the channel region of the semiconductor layer of the first transistor.

### Claim 17 (depends on 1)

The display device of claim 1, wherein the power supply voltage line and the data line are arranged on a same layer.

### Claim 18 (depends on 17)

The display device of claim 17, wherein the power supply voltage line is arranged on a layer between the light emitting device and the first capacitor.

### Claim 19 (depends on 1)

The display device of claim 1, further comprising a connection electrode electrically connected to the semiconductor layer of the first transistor and the semiconductor layer of the third transistor.

### Claim 20 (depends on 1)

The display device of claim 1, wherein the gate electrode of the first transistor is curved.