# US 11,910,670 B2 · Display substrate and manufacturing method thereof, and compensating method for wire load > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,910,670 B2 - Document ID: US11910670B2 - Status: Granted - Kind: B2 - Application number: 17/429,800 - Filed: 2020-02-27 - Published: 2022-09-29 - Granted: 2024-02-20 - Earliest claimed: 2020-02-27 - Assignees: Chengdu Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Inventors: Yulong Wei; Mengmeng Du; Xiaoqing Shu; Jiping Zhao - Web page: https://patentgrep.com/patent/US11910670B2 ## CPC - G09G 3/3241: the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror - H10K 59/131: Interconnections, e.g. wiring lines or terminals - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/60: wherein the TFTs are in active matrices - G09G 2300/0426: Layout of electrodes and connections - G09G 2310/0264: Details of driving circuits - G09G 2320/0204: Compensation of DC component across the pixels in flat panels - G09G 2320/0233: Improving the luminance or brightness uniformity across the screen - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A display substrate and a manufacturing method thereof, and a compensating method for wire load are provided. The display substrate includes a display region and a peripheral region. The display region has an opening, and the peripheral region includes an opening peripheral region at least partially in the opening; at least one wire is provided in the display region and the opening peripheral region. Each of the at least one wire includes two portions, a first portion is spaced apart and insulated from the semiconductor pattern and the conductive pattern, to provide at least one first compensation unit, and a second portion is spaced apart and insulated from one of the semiconductor pattern and the conductive pattern, to provide at least one second compensation unit. ## Claims ### Claim 1 A display substrate, having a display region and a peripheral region at least partially surrounding the display region, and comprising: a base substrate, a semiconductor pattern, at least one wire, and a conductive pattern, wherein the display region has an opening, and the peripheral region comprises an opening peripheral region at least partially in the opening; the semiconductor pattern and the conductive pattern are on the base substrate and in the opening peripheral region; the at least one wire is in the display region and the opening peripheral region, and is configured to transmit an electrical signal for the display region; each of the at least one wire comprises a first portion and a second portion; and in a direction perpendicular to the base substrate, the first portion is spaced apart and insulated from the semiconductor pattern and the conductive pattern, to provide at least one first compensation unit with a first capacitor structure, and the second portion is spaced apart and insulated from one of the semiconductor pattern and the conductive pattern, to provide at least one second compensation unit with a second capacitor structure. ### Claim 2 (depends on 1) The display substrate according to claim 1, wherein the at least one wire is on a side of the semiconductor pattern away from the base substrate, and the conductive pattern is on a side of the at least one wire away from the semiconductor pattern. ### Claim 3 (depends on 1) The display substrate according to claim 1, wherein in the direction perpendicular to the base substrate, the second portion does not overlap with the semiconductor pattern, so as to allow the second portion to be only spaced apart and insulated from the conductive pattern to provide the second capacitor structure. ### Claim 4 (depends on 1) The display substrate according to claim 1, wherein the display region comprises a first sub-display region and a second sub-display region which are on opposite sides of the opening, the first sub-display region and the second sub-display region respectively comprise a plurality of rows of sub-pixels separated by the opening, and the at least one wire sequentially passes through the first sub-display region, the opening peripheral region, and the second sub-display region; and the at least one wire comprises a first wire for providing a scanning signal for a first sub-pixel row in the first sub-display region and the second sub-display region, and further comprises a second wire for providing a scanning signal for a second sub-pixel row in the first sub-display region and the second sub-display region. ### Claim 5 (depends on 4) The display substrate according to claim 4, wherein a count of sub-pixels comprised in the first sub-pixel row is identical to a count of sub-pixels comprised in the second sub-pixel row, a count of first compensation units comprised in the first wire is identical to a count of first compensation units comprised in the second wire, and a count of second compensation units comprised in the first wire is identical to a count of second compensation units comprised in the second wire. ### Claim 6 (depends on 4) The display substrate according to claim 4, wherein a count of sub-pixels comprised in the first sub-pixel row is different from a count of sub-pixels comprised in the second sub-pixel row; and a count of first compensation units comprised in the first wire is different from a count of first compensation units comprised in the second wire, or a count of second compensation units comprised in the first wire is different from a count of second compensation units comprised in the second wire, or the count of first compensation units comprised in the first wire is different from the count of first compensation units comprised in the second wire, and the count of second compensation units comprised in the first wire is different from the count of second compensation units comprised in the second wire. ### Claim 7 (depends on 4) The display substrate according to claim 4, wherein the display region further comprises a third sub-display region, the first sub-display region, the opening, and the second sub-display region are arranged sequentially in a first direction, the at least one wire extends along the first direction, and the second direction is perpendicular to the first direction; two opposite edges of the third sub-display region in the second direction are respectively aligned with an edge, away from the opening in the second direction, of the first sub-display region, and an edge, away from the opening in the second direction, of the second sub-display region; and the third sub-display region comprises sub-pixels arranged in a plurality of rows and a plurality of columns, and further comprises a plurality of third wires providing a scanning signal for each row of the sub-pixels arranged in the plurality of rows and the plurality of columns and extending along the first direction. ### Claim 8 (depends on 7) The display substrate according to claim 7, wherein the semiconductor pattern comprises a plurality of semiconductor wires extending along the second direction, and the conductive pattern is continuously provided on a side of the at least one wire away from the semiconductor pattern. ### Claim 9 (depends on 8) The display substrate according to claim 8, wherein a line width of the at least one wire ranges from 3 μm to 5 μm, and a line width of the semiconductor pattern ranges from 20 μm to 30 μm. ### Claim 10 (depends on 1) The display substrate according to claim 1, further comprising a first insulating layer and a second insulating layer, wherein the first insulating layer is on a side of the semiconductor pattern away from the base substrate, the at least one wire is on a side of the first insulating layer away from the semiconductor pattern, and the second insulating layer is on a side of the at least one wire away from the first insulating layer, and the conductive pattern is on a side of the second insulating layer away from the at least one wire; and the first insulating layer and the second insulating layer have a via, and the semiconductor pattern is electrically connected to the conductive pattern through the via in the first insulating layer and the second insulating layer. ### Claim 11 (depends on 10) The display substrate according to claim 10, wherein the display region further comprises a first power line electrically connected to the pixel circuit, and the power wire pattern and the first power line are provided in an identical layer. ### Claim 12 (depends on 1) The display substrate according to claim 1, further comprising a power wire pattern electrically connected to the conductive pattern, wherein the power wire pattern is configured to provide an electrical signal for the conductive pattern. ### Claim 13 (depends on 12) The display substrate according to claim 12, wherein the display region comprises a plurality of sub-pixels, and each of the sub-pixels comprises a pixel circuit; and the pixel circuit comprises a thin film transistor, the thin film transistor comprises an active layer, a gate electrode, a source electrode, and a drain electrode, and the semiconductor pattern and the active layer are provided in an identical layer. ### Claim 14 (depends on 13) The display substrate according to claim 13, wherein the pixel circuit further comprises a storage capacitor, and the storage capacitor comprises a first capacitor plate and a second capacitor plate; and the gate electrode and the first capacitor plate are provided in an identical layer, and the at least one wire and the second capacitor plate are provided in an identical layer. ### Claim 15 (depends on 13) The display substrate according to claim 13, wherein the conductive pattern, the source electrode, and the drain electrode are provided in an identical layer. ### Claim 16 (depends on 12) The display substrate according to claim 12, wherein each of the sub-pixels further comprises a light-emitting element, the light-emitting element comprises a cathode, an anode, and a light-emitting layer between the cathode and the anode, at least one of the cathode and the anode is electrically connected to the pixel circuit, and the power wire pattern and the anode are provided in an identical layer. ### Claim 17 A compensating method for wire load, comprising: providing at least one first compensation unit and at least one second compensation unit for a wire, and preliminarily determining a count of the at least one first compensation unit and a count of the at least one second compensation unit; obtaining a load of the wire, and comparing the load of the wire with a reference load to obtain a compensation deviation; and redesigning the count of the at least one first compensation unit and the count of the at least one second compensation unit according to the compensation deviation, wherein a display region has an opening, a peripheral region at least partially surrounds the display region, the peripheral region comprises an opening peripheral region at least partially in the opening, the wire is in the display region and the opening peripheral region and is configured to transmit an electrical signal for the display region, opposite sides of the wire are provided with a semiconductor pattern and a conductive pattern, the wire comprises a first portion and a second portion, the first portion is spaced apart and insulated from the semiconductor pattern and the conductive pattern, to provide the at least one first compensation unit with a first capacitor structure, and the second portion is spaced apart and insulated from one of the semiconductor pattern and the conductive pattern, to provide the at least one second compensation unit with a second capacitor structure. ### Claim 18 A manufacturing method of a display substrate, comprising: forming a display region and a peripheral region at least partially surrounding the display region, wherein an opening is formed in the display region, and the peripheral region comprises an opening peripheral region at least partially in the opening; the display substrate comprises a base substrate, a semiconductor pattern, at least one wire, and a conductive pattern; the semiconductor pattern and the conductive pattern are formed on the base substrate and in the opening peripheral region, the at least one wire is formed in the display region and the opening peripheral region, and is configured to transmit an electrical signal for the display region; each of the at least one wire comprises a first portion and a second portion; and in a direction perpendicular to the base substrate, the first portion is spaced apart and insulated from the semiconductor pattern and the conductive pattern, to provide at least one first compensation unit with a first capacitor structure, and the second portion is spaced apart and insulated from one of the semiconductor pattern and the conductive pattern, to provide at least one second compensation unit with a second capacitor structure. ### Claim 19 (depends on 18) The manufacturing method of the display substrate according to claim 18, wherein the at least one wire is formed on a side of the semiconductor pattern away from the base substrate; the conductive pattern is formed on a side of the at least one wire away from the semiconductor pattern; and in the direction perpendicular to the base substrate, the second portion does not overlap with the semiconductor pattern, so as to allow the second portion to be only spaced apart and insulated from the conductive pattern to provide the second capacitor structure. ### Claim 20 (depends on 19) The manufacturing method of the display substrate according to claim 19, further comprising: forming a first insulating layer and a second insulating layer, wherein the first insulating layer is formed on a side of the semiconductor pattern away from the base substrate, the at least one wire is formed on a side of the first insulating layer away from the semiconductor pattern, the second insulating layer is formed on a side of the at least one wire away from the first insulating layer, and the conductive pattern is formed on a side of the second insulating layer away from the at least one wire; and the first insulating layer and the second insulating layer have a via, and the semiconductor pattern is electrically connected to the conductive pattern through the via in the first insulating layer and the second insulating layer.