# US 11,910,667 B2 · Display apparatus and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,910,667 B2 - Document ID: US11910667B2 - Status: Granted - Kind: B2 - Application number: 17/407,399 - Filed: 2021-08-20 - Published: 2022-06-16 - Granted: 2024-02-20 - Earliest claimed: 2020-12-14 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Jaewon Cho; Wonmi Hwang; Geurim Lee; Changwon Jeong - Web page: https://patentgrep.com/patent/US11910667B2 ## CPC - H10K 59/124: Insulating layers formed between TFT elements and OLED elements - H10K 59/131: Interconnections, e.g. wiring lines or terminals - H10K 59/1201: {Manufacture or treatment} - H10K 59/80518: {Reflective anodes, e.g. ITO combined with thick metallic layers} - H10K 2102/341: {Short-circuit prevention} - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract A display apparatus includes a substrate including a display area and a peripheral area disposed outside the display area, a transistor disposed in the display area on the substrate, a first pad part disposed in the peripheral area on the substrate, a second pad part disposed in the peripheral area on the substrate and spaced apart from the first pad part, a first pad disposed in the second pad part, a second pad disposed in the second pad part and spaced apart from the first pad and a passivation layer including a plurality of grooves defined between the first pad and the second pad and a protrusion disposed between two adjacent grooves among the grooves. ## Claims ### Claim 1 A display apparatus comprising: a substrate including a display area and a peripheral area disposed outside the display area; a transistor disposed in the display area on the substrate; a first pad part disposed in the peripheral area on the substrate; a second pad part disposed in the peripheral area on the substrate and spaced apart from the first pad part; a first pad disposed in the second pad part; a second pad disposed in the second pad part and spaced apart from the first pad; and a passivation layer including a plurality of grooves defined between the first pad and the second pad and a protrusion disposed between two adjacent grooves among the grooves. ### Claim 2 (depends on 1) The display apparatus of claim 1, wherein the passivation layer includes: an insulation interlayer including an inorganic material; and an insulation layer disposed on the insulation interlayer and including an organic material. ### Claim 3 (depends on 2) The display apparatus of claim 2, wherein an edge of each of the first pad and the second pad overlaps the insulation layer. ### Claim 4 (depends on 1) The display apparatus of claim 1, wherein the protrusion includes at least one selected from an organic material and an inorganic material. ### Claim 5 (depends on 1) The display apparatus of claim 1, wherein a lower surface of each of the grooves is disposed under a lower surface of the first pad and a lower surface of the second pad. ### Claim 6 (depends on 1) The display apparatus of claim 1, wherein a width of a lower surface of each of the grooves is in a range from about 3 micrometers to about 11.5 micrometers. ### Claim 7 (depends on 1) The display apparatus of claim 1, wherein an interval between the two adjacent grooves is in a range from about 3 micrometers to about 20 micrometers. ### Claim 8 (depends on 1) The display apparatus of claim 1, wherein the transistor includes: a semiconductor layer including a channel region, a source region and a drain region; a gate insulation layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulation layer; an insulation interlayer disposed on the gate electrode; a source electrode disposed on the insulation interlayer and connected to the source region; and a drain electrode disposed on the insulation interlayer and connected to the drain region, and wherein the first pad and the second pad are disposed on the insulation interlayer. ### Claim 9 (depends on 8) The display apparatus of claim 8, wherein the first pad and the second pad include a same material as the source electrode and the drain electrode. ### Claim 10 (depends on 1) The display apparatus of claim 1, wherein the first pad part is connected to a driving chip, and wherein the second pad part is connected to a flexible circuit board. ### Claim 11 (depends on 1) The display apparatus of claim 1, wherein the first pad and the second pad receive different voltages from each other. ### Claim 12 A display apparatus comprising: a substrate including a display area and a peripheral area disposed outside the display area; a pad part disposed in the peripheral area on the substrate and including a first area including an organic material and a second area disposed outside the first area; a wiring part overlapping the second area and including a first wiring and a second wiring; and a passivation layer including a plurality of grooves defined between the first wiring and the second wiring and at a protrusion disposed between two adjacent grooves among the grooves. ### Claim 13 (depends on 12) The display apparatus of claim 12, wherein the passivation layer includes an insulation interlayer disposed under the first wiring and the second wiring. ### Claim 14 (depends on 12) The display apparatus of claim 12, wherein the protrusion includes an inorganic material. ### Claim 15 (depends on 12) The display apparatus of claim 12, wherein a lower surface of the groove is disposed under a lower surface of the first wiring and a lower surface of the second wiring. ### Claim 16 A method of manufacturing a display apparatus, the method comprising: providing an insulation interlayer on a substrate, wherein the insulation interlayer includes a first groove and a second groove; providing a first pad and a second pad on the insulation interlayer with the first groove and the second groove disposed therebetween; providing an insulation layer on the first pad and the second pad; and forming a third groove overlapping the first groove and a fourth groove overlapping the second groove in the insulation layer. ### Claim 17 (depends on 16) The method of claim 16, further comprising, providing a transistor on the substrate, wherein the transistor includes a semiconductor layer including a channel region, a source region and a drain region, a gate insulation layer formed on the semiconductor layer, a gate electrode formed on the gate insulation layer, an insulation interlayer formed on the gate electrode, wherein a first contact hole is formed through the insulation interlayer to overlap the source region and a second contact hole is formed through the insulation interlayer to overlap the drain region, a source electrode formed on the insulation interlayer and connected to the source region, and a drain electrode formed on the insulation interlayer and connected to the drain region, wherein the source electrode, the drain electrode, the first pad and the second pad are simultaneously formed with each other. ### Claim 18 (depends on 17) The method of claim 17, wherein a third contact hole is formed through the insulation layer further to overlap the source electrode or the drain electrode, wherein the first contact hole, the second contact hole, the first groove and the second groove are simultaneously formed with each other, and wherein the third contact hole, the third groove and the fourth groove are simultaneously formed with each other. ### Claim 19 (depends on 17) The method of claim 17, wherein the first pad and the second pad include a same material as the source electrode and the drain electrode. ### Claim 20 (depends on 16) The method of claim 16, wherein an edge of each of the first pad and the second pad overlaps the insulation layer.