# US 11,910,622 B1 · 3D memory semiconductor devices and structures with bit-line pillars > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,910,622 B1 - Document ID: US11910622B1 - Status: Granted - Kind: B1 - Application number: 18/384,304 - Filed: 2023-10-26 - Published: 2024-02-22 - Granted: 2024-02-20 - Earliest claimed: 2019-04-08 - Assignees: Monolithic 3D Inc. - Applicants: Monolithic 3D Inc. - Inventors: Zvi Or-Bach; Jin-Woo Han; Eli Lusky - Web page: https://patentgrep.com/patent/US11910622B1 ## CPC - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C 16/0416: {comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM} - G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/24: Bit-line control circuits - H10B 41/10: characterised by the top-view layout - H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 41/40: characterised by the peripheral circuit region - H10B 43/10: characterised by the top-view layout - H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/30: characterised by the memory core region - H10B 43/40: characterised by the peripheral circuit region - H10W 80/00: Direct bonding of chips, wafers or substrates - H10W 90/00: Package configurations - G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines - G11C 7/18: Bit line organisation; Bit line lay-out - G11C 16/10: Programming or data input circuits - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/26: Sensing or reading circuits; Data output circuits - H10W 90/792: {between multiple chips} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A 3D memory device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of memory-line pillars, where each memory-line pillar of the plurality of memory-line pillars is directly connected to a plurality of the source or the drain, where the plurality of memory-line pillars are vertically oriented, where the channel is horizontally-oriented and a plurality are connected to a body pillar, where the body pillar is at least temporary connected to a negative bias, the at least one memory transistor is self-aligned to an overlaying another memory transistor, both being processed following a same lithography step; a control level including a memory controller circuit and is hybrid bonded to the first structure. ## Claims ### Claim 1 A 3D memory device, the device comprising: a first structure comprising a plurality of memory cells, wherein each memory cell of said plurality of memory cells comprises at least one memory transistor, wherein each of said at least one memory transistor comprises a source, a drain, and a channel; a plurality of memory-line pillars, wherein each memory-line pillar of said plurality of memory-line pillars is directly connected to a plurality of said source or said drain, wherein said plurality of memory-line pillars are vertically oriented, wherein said channel is horizontally oriented, wherein a plurality of said channel are connected to a body pillar, wherein said body pillar is at least temporary connected to a negative bias, wherein said at least one memory transistor is self-aligned to an overlaying another said at least one memory transistor, both being processed following a same lithography step; and a control level comprising a memory controller circuit, wherein said control level is bonded to said first structure, and wherein said bonded comprises hybrid bonding. ### Claim 2 (depends on 1) The device according to claim 1, wherein each memory cell of said plurality of memory cells comprises a charge trap memory, wherein said channel comprises polysilicon, wherein said source and/or said drain comprises metal atoms, and wherein said metal atoms enable hot electron programming of said charge trap memory. ### Claim 3 (depends on 1) The device according to claim 1, wherein each of said at least one memory transistor is directly connected to at least one of said plurality of memory-line pillars. ### Claim 4 (depends on 1) The device according to claim 1, wherein said plurality of memory cells comprise a partially or fully metalized source, and/or, a partially or fully metalized drain. ### Claim 5 (depends on 1) The device according to claim 1, wherein at least one of said plurality of said memory cells comprise a tunneling oxide thinner than 1 nm. ### Claim 6 (depends on 1) The device according to claim 1, wherein said memory controller circuit is capable to perform a self-differential read cycle. ### Claim 7 (depends on 1) The device according to claim 1, wherein said memory controller circuit comprises a row buffer. ### Claim 8 A 3D memory device, the device comprising: a first structure comprising a plurality of memory cells, wherein each memory cell of said plurality of memory cells comprises at least one memory transistor, wherein each of said at least one memory transistor comprises a source, a drain, and a channel; a plurality of memory-line pillars, wherein each memory-line pillar of said plurality of memory-line pillars is directly connected to a plurality of said source or said drain, wherein said plurality of memory-line pillars are vertically oriented, wherein said at least one memory transistor is self-aligned to an overlaying another said at least one memory transistor, both being processed following a same lithography step; and a control level comprising a memory controller circuit, wherein said memory controller circuit comprises a row buffer, wherein said control level is bonded to said first structure, and wherein said bonded comprises hybrid bonding. ### Claim 9 (depends on 8) The device according to claim 8, wherein each memory cell of said plurality of memory cells comprises a charge trap memory, wherein said channel comprises polysilicon, wherein said channel is horizontally oriented, wherein said source and/or said drain comprises metal atoms, and wherein said metal atoms enable hot electron programming of said charge trap memory. ### Claim 10 (depends on 8) The device according to claim 8, wherein each of said at least one memory transistor is directly connected to at least one of said plurality of memory-line pillars. ### Claim 11 (depends on 8) The device according to claim 8, wherein a plurality of said channels are connected to a body pillar, and wherein said body pillar is at least temporary connected to a negative bias. ### Claim 12 (depends on 8) The device according to claim 8, wherein at least one of said plurality of said memory cells comprise a tunneling oxide thinner than 1 nm. ### Claim 13 (depends on 8) The device according to claim 8, wherein said memory controller circuit is capable to perform a self-differential read cycle. ### Claim 14 (depends on 8) The device according to claim 8, wherein said plurality of memory cells comprise a partially or fully metalized source, and/or, a partially or fully metalized drain. ### Claim 15 A 3D memory device, the device comprising: a first structure comprising a plurality of memory cells, wherein each memory cell of said plurality of memory cells comprises at least one memory transistor, wherein each of said at least one memory transistor comprises a source, a drain, and a channel; a plurality of memory-line pillars, wherein each memory-line pillar of said plurality of memory-line pillars is directly connected to a plurality of said source or said drain, wherein said plurality of memory-line pillars are vertically oriented, wherein said at least one memory transistor is self-aligned to an overlaying another said at least one memory transistor, both being processed following a same lithography step; and a control level comprising a memory controller circuit, wherein said control level is adapted to perform a preset operation, wherein said control level is bonded to said first structure, and wherein said bonded comprises hybrid bonding. ### Claim 16 (depends on 15) The device according to claim 15, wherein each memory cell of said plurality of memory cells comprises a charge trap memory, wherein said channel comprises polysilicon, wherein said channel is horizontally oriented, wherein said source and/or said drain comprises metal atoms, and wherein said metal atoms enable hot electron programming of said charge trap memory. ### Claim 17 (depends on 15) The device according to claim 15, wherein each of said at least one memory transistor is directly connected to at least one of said plurality of memory-line pillars. ### Claim 18 (depends on 15) The device according to claim 15, wherein said controller circuit comprises a row buffer. ### Claim 19 (depends on 15) The device according to claim 15, wherein said memory controller circuit is capable to perform a self-differential read cycle. ### Claim 20 (depends on 15) The device according to claim 15, wherein said plurality of memory cells comprise a partially or fully metalized source, and/or, a partially or fully metalized drain.