# US 11,910,618 B1 · Multi-element ferroelectric gain memory bit-cell having stacked and folded non-planar capacitors

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- Number: US 11,910,618 B1
- Document ID: US11910618B1
- Status: Granted
- Kind: B1
- Application number: 17/654,562
- Filed: 2022-03-11
- Granted: 2024-02-20
- Earliest claimed: 2022-03-07
- Assignees: Kepler Computing Inc.
- Applicants: Kepler Computing Inc.
- Inventors: Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
- Web page: https://patentgrep.com/patent/US11910618B1

## CPC

- H10B 53/30: characterised by the memory core region
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 11/1659: {Cell access}
- G11C 11/221: {using ferroelectric capacitors}
- G11C 11/223: {using MOS with ferroelectric gate insulating film}
- G11C 11/2255: {Bit-line or column circuits}
- G11C 11/2257: {Word-line or row circuits}
- G11C 11/2273: {Reading or sensing circuits or methods}
- G11C 11/2275: {Writing or programming circuits or methods}
- G11C 11/2293: {Timing circuits or methods}
- G11C 11/419: Read-write [R-W] circuits
- G11C 13/003: {Cell access}
- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- H10B 12/48: {Data lines or contacts therefor}
- H10B 53/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B 53/10: characterised by the top-view layout
- H10B 53/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10D 1/682: {having dielectrics comprising perovskite structures}
- H10D 1/696: {comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688)}
- H10W 90/00: Package configurations
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 11/2259: {Cell access}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 2213/52: Structure characterized by the electrode material, shape, etc.
- G11C 2213/71: Three dimensional array
- G11C 2213/74: Array wherein each memory cell has more than one access device
- G11C 2213/78: Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
- G11C 2213/79: Array wherein the access device being a transistor
- H10N 50/10: Magnetoresistive devices
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

## Claims

### Claim 1

An apparatus comprising:
a first transistor having a first gate terminal coupled to a word-line, a first source terminal coupled to a bit-line, and a first drain terminal coupled to a storage node;
a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal coupled to a sense line, and a second drain terminal coupled to a bias; and
a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line, and wherein the plurality of capacitors are non-planar capacitors that are arranged in a stacked and folded configuration.

### Claim 2 (depends on 1)

The apparatus of claim 1 comprising:
a first conductive electrode directly connected to the storage node, wherein the first conductive electrode extends vertically away from the storage node; and
a second conductive electrode directly connected to the storage node, wherein the second conductive electrode extends vertically away from the storage node, and wherein the first conductive electrode and the second conductive electrode are substantially parallel.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the plurality of capacitors includes:
a first set of capacitors adjacent to the first conductive electrode; and
a second set of capacitors adjacent to the second conductive electrode.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the first set of capacitors includes a first capacitor which includes:
a first layer coupled to the first conductive electrode, wherein the first layer comprises a first metal;
a second layer around the first layer, wherein the second layer comprises a first conductive oxide;
a third layer comprising a ferroelectric dielectric material, wherein the third layer is around the second layer;
a fourth layer around the third layer, wherein the fourth layer comprises a second conductive oxide, and wherein the fourth layer is around the third layer; and
a fifth layer around the fourth layer, wherein the fifth layer comprises a second metal, wherein a first node is adjacent to part of the fifth layer, and wherein the first node is coupled to a first switch.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein:
the first layer has a first circumference;
the second layer has a second circumference;
the third layer has a third circumference;
the fourth layer has a fourth circumference; and
the fifth layer has a fifth circumference, wherein the fifth circumference is larger than the fourth circumference, wherein the fourth circumference is larger than the third circumference, wherein the third circumference is larger than the second circumference, and wherein the second circumference is larger than the first circumference.

### Claim 6 (depends on 3)

The apparatus of claim 3, wherein the second set of capacitors includes a second capacitor which includes:
a first layer coupled to the second conductive electrode, wherein the first layer comprises a first metal;
a second layer around the first layer, wherein the second layer comprises a first conductive oxide;
a third layer comprising a ferroelectric dielectric material, wherein the third layer is around the second layer;
a fourth layer around the third layer, wherein the fourth layer comprises a second conductive oxide, and wherein the fourth layer is around the third layer; and
a fifth layer around the fourth layer, wherein the fifth layer comprises a second metal, wherein a second node is adjacent to part of the fifth layer, and wherein the second node is coupled to a second switch.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein:
the first layer has a first circumference;
the second layer has a second circumference;
the third layer has a third circumference;
the fourth layer has a fourth circumference; and
the fifth layer has a fifth circumference, wherein the fifth circumference is larger than the fourth circumference, wherein the fourth circumference is larger than the third circumference, wherein the third circumference is larger than the second circumference, and wherein the second circumference is larger than the first circumference.

### Claim 8 (depends on 4)

The apparatus of claim 4, wherein the plurality of capacitors has N capacitors divided in L number of conductive electrodes such that there are N/L capacitors in an individual conductive electrode.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the N/L capacitors are shorted together through the individual conductive electrode.

### Claim 10 (depends on 3)

The apparatus of claim 3, wherein the first conductive electrode or the second conductive electrode comprises metal, a first conducting oxide, or a combination of a second conducting oxide and an insulative material.

### Claim 11 (depends on 3)

The apparatus of claim 3, wherein the first conductive electrode is a first shared bottom electrode for the first set of capacitors, and wherein the second conductive electrode is a second shared bottom electrode for the second set of capacitors.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the individual capacitor includes a top electrode which is partially coupled to an individual node, and wherein the individual node is coupled to the individual plate-line via an individual switch.

### Claim 13 (depends on 1)

The apparatus of claim 1, wherein the individual plate-line is parallel to the bit-line.

### Claim 14 (depends on 1)

The apparatus of claim 1, wherein the plurality of capacitors comprises non-linear polar material.

### Claim 15

An apparatus comprising:
a first transistor having a first gate terminal coupled to a word-line, a first source terminal coupled to a bit-line, and a first drain terminal coupled to a storage node;
a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal couple to a sense line, and a second drain terminal coupled to a bias;
a plurality of bottom electrodes extending vertically compared to lateral side of the first transistor, wherein the plurality of bottom electrodes is coupled to the storage node; and
a plurality of capacitors having a first terminal coupled to the plurality of bottom electrodes, wherein a second terminal of an individual capacitor of the plurality of capacitors is partially coupled to an individual plate-line, and wherein the plurality of capacitors are non-planar capacitors.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the plurality of bottom electrodes comprises:
a first conductive electrode directly connected to the storage node, wherein the first conductive electrode extends vertically away from the storage node; and
a second conductive electrode directly connected to the storage node, wherein the second conductive electrode extends vertically away from the storage node, and wherein the first conductive electrode and the second conductive electrode are substantially parallel.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the plurality of capacitors include:
a first set of capacitors having a first layer adjacent to the first conductive electrode; and
a second set of capacitors having a second layer adjacent to the second conductive electrode.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the first set of capacitors includes a first capacitor which includes:
a first layer coupled to the first conductive electrode, wherein the first layer comprises a first metal;
a second layer around the first layer, wherein the second layer comprises a first conductive oxide;
a third layer comprising a ferroelectric dielectric material, wherein the third layer is around the second layer;
a fourth layer around the third layer, wherein the fourth layer comprises a second conductive oxide, wherein the fourth layer is around the third layer; and
a fifth layer around the fourth layer, wherein the fifth layer comprises a second metal, wherein a first node is adjacent to part of the fifth layer, and wherein the first node is coupled to a first switch.

### Claim 19

A system comprising:
a processor circuitry to execute one or more instructions;
a memory circuitry to store the one or more instructions; and
a communication interface to allow the processor circuitry to communicate with another device, wherein the memory circuitry includes a plurality of bit-cells organized in a memory array, and wherein an individual bit-cell of the plurality of bit-cells includes:
a first transistor having a first gate terminal coupled to a word-line, a first source terminal coupled to a bit-line, and a first drain terminal coupled to a storage node;
a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal coupled to a sense line, and a second drain terminal coupled to a bias; and
a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line, and wherein the plurality of capacitors are non-planar capacitors that are arranged in a stacked and folded configuration.

### Claim 20 (depends on 19)

The system of claim 19, wherein the individual bit-cell includes:
a first conductive electrode directly connected to the storage node, wherein the first conductive electrode extends vertically away from the storage node; and
a second conductive electrode directly connected to the storage node, wherein the second conductive electrode extends vertically away from the storage node, and wherein the first conductive electrode and the second conductive electrode are substantially parallel.