# US 11,910,617 B2 · Ferroelectric memory device and method of forming the same

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- Number: US 11,910,617 B2
- Document ID: US11910617B2
- Status: Granted
- Kind: B2
- Application number: 17/098,919
- Filed: 2020-11-16
- Published: 2021-12-02
- Granted: 2024-02-20
- Earliest claimed: 2020-05-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chun-Chieh Lu; Han-Jong Chia; Sai-Hooi Yeong; Bo-Feng Young; Yu-Ming Lin
- Web page: https://patentgrep.com/patent/US11910617B2

## CPC

- H10B 51/30: characterised by the memory core region
- H10D 64/033: {comprising ferroelectric layers}
- H10B 51/10: characterised by the top-view layout
- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10B 51/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.

## Claims

### Claim 1

A method of forming a ferroelectric memory device, comprising:
forming a multi-layer stack and comprising a plurality of dielectric layers and a plurality of conductive layers stacked alternately over a substrate, wherein sidewalls of the plurality of dielectric layers and the plurality of conductive layers define a trench penetrating therethrough;
selectively forming a plurality of ferroelectric portions discretely on the sidewalls of the plurality of conductive layers;
after forming the plurality of ferroelectric portions then forming a channel layer on the plurality of ferroelectric portions and the sidewalls of the plurality of dielectric layers; and
forming a conductive pillar along sidewalls of the channel layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the selectively forming the plurality of ferroelectric portions comprises:
performing a surface treatment on sidewall surfaces of the plurality of dielectric layers; and
depositing the plurality of ferroelectric portions on the sidewalls of the plurality of conductive layers.

### Claim 3 (depends on 2)

The method of claim 2, wherein the performing the surface treatment comprises selectively forming a plurality of inhibitor portions on the sidewall surfaces of the plurality of dielectric layers.

### Claim 4 (depends on 3)

The method of claim 3, wherein the plurality of inhibitor portions comprises a plurality of self-assembled monolayers.

### Claim 5 (depends on 4)

The method of claim 4, wherein the plurality of self-assembled monolayers comprise an alkanethiol, an alkanephophonic acid or a combination thereof.

### Claim 6 (depends on 4)

The method of claim 4, wherein the plurality of self-assembled monolayers comprise 1-octadecanethiol (ODT), or octadecylphophonic acid (ODPA).

### Claim 7 (depends on 4)

The method of claim 4, wherein the channel layer is formed to be directly between horizontally extending surfaces of vertically adjacent ones of the plurality of ferroelectric portions.

### Claim 8

A method of forming a ferroelectric memory device, comprising:
forming a multi-layer stack over a substrate, the multi-layer stack comprising a plurality of dielectric layers interleaved between a plurality of conductive layers;
patterning the multi-layer stack to form a trench extending through the multi-layer stack;
forming a plurality of self-assembled monolayers on sidewalls of the plurality of dielectric layers exposed by the trench;
forming a plurality of ferroelectric segments on sidewalls of the plurality of conductive layers and vertically outside of the plurality of self-assembled monolayers;
forming a channel layer directly on upper surfaces, lower surfaces, or sidewalls of the plurality of ferroelectric segments and the sidewalls of the plurality of dielectric layers; and
forming a conductive pillar along sidewalls of the channel layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the channel layer physically contacts the upper surfaces, the lower surfaces, and the sidewalls of the plurality of ferroelectric segments.

### Claim 10 (depends on 8)

The method of claim 8, wherein the plurality of ferroelectric segments are entirely laterally outside of the plurality of dielectric layers.

### Claim 11 (depends on 10)

The method of claim 10, wherein the channel layer is further in contact with the plurality of dielectric layers.

### Claim 12 (depends on 8)

The method of claim 8, wherein the plurality of ferroelectric segments have a crystalline structure with an orthorhombic phase of more than 80 mol %.

### Claim 13 (depends on 8)

The method of claim 8, wherein the conductive pillar comprises:
a plurality of first portions laterally adjacent to the plurality of dielectric layers; and
a plurality of second portions laterally adjacent to the plurality of conductive layers, wherein the plurality of first portions and the plurality of second portions have different widths.

### Claim 14 (depends on 13)

The method of claim 13, wherein the channel layer is sandwiched between the plurality of dielectric layers and the plurality of first portions of the conductive pillar, and sandwiched between the plurality of ferroelectric segments and the plurality of second portions of the conductive pillar.

### Claim 15 (depends on 13)

The method of claim 13, wherein the channel layer is formed after forming the plurality of ferroelectric segments.

### Claim 16

A method of forming a ferroelectric memory device, comprising:
forming a multi-layer stack over a substrate, the multi-layer stack comprising a plurality of dielectric layers interleaved between a plurality of conductive layers, wherein sidewalls of the plurality of dielectric layers and the plurality of conductive layers define a trench penetrating therethrough;
forming a plurality of ferroelectric portions on the sidewalls of the plurality of conductive layers;
forming a channel layer on the plurality of ferroelectric portions and the sidewalls of the plurality of dielectric layers, wherein the channel layer is formed to have a sidewall that contacts the sidewalls of the plurality of dielectric layers and an adjoining upper surface that contacts a lower surface of the plurality of ferroelectric portions, the lower surface of the plurality of ferroelectric portions facing the substrate; and
forming a conductive pillar along sidewalls of the channel layer, wherein the conductive pillar is formed to have a wavy sidewall profile.

### Claim 17 (depends on 16)

The method of claim 16, wherein the channel layer is formed on an upper surface and a lower surface of respective ones of the plurality of ferroelectric portions.

### Claim 18 (depends on 16)

The method of claim 16, wherein the channel layer is formed onto the plurality of ferroelectric portions after forming the plurality of ferroelectric portions onto the sidewalls of the plurality of conductive layers.

### Claim 19 (depends on 16)

The method of claim 16, wherein the conductive pillar is formed to comprise:
a plurality of first portions laterally separated from the plurality of dielectric layers by the channel layer; and
a plurality of second portions laterally separated from the plurality of conductive layers by the channel layer, wherein the plurality of first portions and the plurality of second portions have different widths.

### Claim 20 (depends on 16)

The method of claim 16, wherein the channel layer comprises an oxide semiconductor.