# US 11,910,615 B2 · Memory device and manufacturing method thereof

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- Number: US 11,910,615 B2
- Document ID: US11910615B2
- Status: Granted
- Kind: B2
- Application number: 17/327,752
- Filed: 2021-05-23
- Published: 2022-07-21
- Granted: 2024-02-20
- Earliest claimed: 2021-01-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Meng-Han Lin; Han-Jong Chia; Feng-Cheng Yang; Bo-Feng Young; Nuo Xu; Sai-Hooi Yeong; Yu-Ming Lin
- Web page: https://patentgrep.com/patent/US11910615B2

## CPC

- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 51/10: characterised by the top-view layout
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory device including a word line, a source line, a bit line, a memory layer, a channel material layer is described. The word line extends in a first direction, and liner layers disposed on a sidewall of the word line. The memory layer is disposed on the sidewall of the word line between the liner layers and extends along sidewalls of the liner layers in the first direction. The liner layers are spaced apart by the memory layer, and the liner layers are sandwiched between the memory layer and the word line. The channel material layer is disposed on a sidewall of the memory layer. A dielectric layer is disposed on a sidewall of the channel material layer. The source line and the bit line are disposed at opposite sides of the dielectric layer and disposed on the sidewall of the channel material layer. The source line and the bit line extend in a second direction perpendicular to the first direction. A material of the liner layers has a dielectric constant lower than that of a material of the memory layer.

## Claims

### Claim 1

A memory device, comprising:
a multilayered stack disposed over a dielectric structure, the multilayered stack comprising first conductive layers and first dielectric layers stacked in alternation;
a second dielectric layer, disposed over the dielectric structure and penetrating through the first conductive layers and the first dielectric layers;
a first conductive line and a second conductive line disposed at opposite sides of the second dielectric layer;
a pair of dielectric blocks respectively disposed alongside the first conductive line and the second conductive line;
a memory layer, disposed between the pair of dielectric blocks and penetrating through the first conductive layers and the first dielectric layers; and
a channel material layer, disposed between the pair of dielectric blocks, extending vertically along the memory layer, and disposed between the first and second conductive lines and the memory layer,
wherein each of the pair of dielectric blocks has an extended portion located between the memory layer and one of the first conductive layers, and a material of the pair of dielectric blocks has a dielectric constant lower than that of a material of the memory layer.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the memory layer comprises a ferroelectric layer.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein a material of the ferroelectric layer includes hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO), undoped hafnium oxide (HfO) or HfO doped with lanthanum (La), silicon (Si), or aluminum (Al).

### Claim 4 (depends on 2)

The memory device of claim 2, wherein a material of the pair of the dielectric blocks includes a low-k dielectric material having a dielectric constant less than 3.9.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the memory layer located between the pair of dielectric blocks extends from one of the pair of dielectric blocks to the other of the pair of dielectric blocks with a first length along an extending direction.

### Claim 6 (depends on 5)

The memory device of claim 5, wherein the channel material layer located between the pair of dielectric blocks extends from one of the pair of dielectric blocks to the other of the pair of dielectric blocks with a second length along the extending direction, and the second length is substantially the same as the first length.

### Claim 7 (depends on 5)

The memory device of claim 5, further comprising a gate dielectric layer located between the channel material layer and the second dielectric layer, wherein the gate dielectric layer extends vertically along the channel material layer and covers sidewalls of portions of the first and second conductive lines and the second dielectric layer.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein the gate dielectric layer extends along the channel material layer and the memory layer in the extending direction with a third length, and the third length is shorter than the first length.

### Claim 9 (depends on 7)

The memory device of claim 7, wherein the first conductive line has a first portion located beside the channel material layer and a second portion located beside the gate dielectric layer, the first portion is located farther from the second dielectric layer and the second portion is in contact with the second dielectric layer.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein the second conductive line has a third portion located beside the channel material layer and a fourth portion located beside the gate dielectric layer, the third portion is located farther from the second dielectric layer and the second portion is in contact with the second dielectric layer.

### Claim 11

A memory device, comprising:
a multilayered stack disposed over a dielectric structure, the multilayered stack comprising first conductive layers and first dielectric layers stacked in alternation;
a second dielectric layer, disposed over the dielectric structure and penetrating through the first conductive layers and the first dielectric layers;
a first conductive line and a second conductive line disposed at opposite sides of the second dielectric layer;
a first dielectric block and a second dielectric block respectively disposed alongside the first conductive line and the second conductive line;
a memory layer, disposed between and extending between the first and second dielectric blocks, and penetrating through the first conductive layers and the first dielectric layers; and
a channel material layer, disposed between and extending between the first and second dielectric blocks, extending vertically along the memory layer, and disposed between the first and second conductive lines and the memory layer,
wherein the first dielectric block has a first extended portion located between the memory layer and one of the first conductive layers, the second dielectric block has a second extended portion between the memory layer and the one of the first conductive layers.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein a material of the first and second dielectric blocks includes a low-k dielectric material and has a dielectric constant lower than that of a material of the memory layer.

### Claim 13 (depends on 11)

The memory device of claim 11, further comprising a gate dielectric layer located between the channel material layer and the second dielectric layer, wherein the gate dielectric layer extends vertically along the channel material layer and covers sidewalls of portions of the first and second conductive lines and the second dielectric layer.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein the gate dielectric layer extends along the channel material layer and covers a portion of the channel material layer.

### Claim 15 (depends on 13)

The memory device of claim 13, wherein the first conductive line has a first portion located beside the channel material layer and a second portion located beside the gate dielectric layer, the first portion is located farther from the second dielectric layer and the second portion is in contact with the second dielectric layer.

### Claim 16 (depends on 15)

The memory device of claim 15, wherein the second conductive line has a third portion located beside the channel material layer and a fourth portion located beside the gate dielectric layer, the third portion is located farther from the second dielectric layer and the second portion is in contact with the second dielectric layer.

### Claim 17

A memory device, comprising:
a multilayered stack disposed over a dielectric structure, the multilayered stack comprising first conductive layers and first dielectric layers stacked in alternation;
a second dielectric layer, disposed over the dielectric structure and penetrating through the first conductive layers and the first dielectric layers;
a first conductive line and a second conductive line disposed at opposite sides of the second dielectric layer;
a first dielectric block and a second dielectric block respectively disposed alongside the first conductive line and the second conductive line, wherein the first dielectric block and the second dielectric block are of a same material including a low-k dielectric material;
a memory layer, disposed between and extending between the first and second dielectric blocks, and penetrating through the first conductive layers and the first dielectric layers; and
a channel material layer, disposed between and extending between the first and second dielectric blocks, extending vertically along the memory layer, and disposed between the first and second conductive lines and the memory layer,
wherein the first dielectric block has a first extended portion located between the memory layer and one of the first conductive layers, the second dielectric block has a second extended portion between the memory layer and the one of the first conductive layers.

### Claim 18 (depends on 17)

The memory device of claim 17, further comprising a gate dielectric layer located between the channel material layer and the second dielectric layer, wherein the gate dielectric layer extends vertically along the channel material layer and covers sidewalls of portions of the first and second conductive lines and the second dielectric layer.

### Claim 19 (depends on 18)

The memory device of claim 18, wherein the first conductive line has a first portion located beside the channel material layer and a second portion located beside the gate dielectric layer, the first portion is located farther from the second dielectric layer and the second portion is in contact with the second dielectric layer.

### Claim 20 (depends on 19)

The memory device of claim 19, wherein the second conductive line has a third portion located beside the channel material layer and a fourth portion located beside the gate dielectric layer, the third portion is located farther from the second dielectric layer and the second portion is in contact with the second dielectric layer.