# US 11,910,612 B2 · Process for forming a vertical thin-film transistor that serves as a connector to a bit-line of a 3-dimensional memory array

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- Number: US 11,910,612 B2
- Document ID: US11910612B2
- Status: Granted
- Kind: B2
- Application number: 17/804,986
- Filed: 2022-06-01
- Published: 2022-09-15
- Granted: 2024-02-20
- Earliest claimed: 2019-02-11
- Assignees: Sunrise Memory Corporation
- Applicants: SunRise Memory Corporation
- Inventors: Tianhong Yan; Scott Brad Herner; Jie Zhou; Wu-Yi Henry Chien; Eli Harari
- Web page: https://patentgrep.com/patent/US11910612B2

## CPC

- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/10: characterised by the top-view layout
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0318: {of vertical TFTs}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6737: {characterised by the electrode materials}
- H10D 30/6743: {Silicon}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3454: {Amorphous}
- H10P 14/414: {of metal-silicide materials}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 32/14: within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P 32/171: {being group IV material}
- H10P 50/283: {by chemical means}
- H10W 20/43: Layouts of interconnections
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

## Claims

### Claim 1

A process for forming a transistor above a planar surface of a substrate, comprising:
Providing first and second conductive layers comprising each a material that is suitable for the first and the second conductive layers to form a drain region and a source region of the transistor, respectively, the first and second conductive layers being isolated from each other by an isolation layer;
providing an active layer in contact with both the first and second conductive layers, wherein the active layer comprises a material suitable for forming a channel region of the transistor and wherein a portion of the active layer is provided above either the first conductive layer or the second conductive layer;
providing a gate dielectric layer over the active layer;
providing a third conductive layer over gate dielectric layer;
etching the active layer, the gate dielectric layer and the third conductive layer to form a line structure around the second conductive layer, the isolation layer and the first conductive layer;
providing a passivation layer to enclose the third conductive layer, the gate dielectric layer, the first and the second conductive layers, the active layer, and the isolation layer;
etching the passivation layer to provide a via to expose a portion of the second conductive layer or a portion of the first conductive layer; and
providing a metallic layer on the exposed portion of second conductive layer or the exposed portion of the first conductive layer.

### Claim 2 (depends on 1)

The process of claim 1, wherein the first and the second conductive layers, and the active layer each comprise a semiconductor material.

### Claim 3 (depends on 2)

The process of claim 2, wherein the active layer or the second conductive layer comprises silicon and wherein the process further comprises annealing the metallic layer to convert the metallic layer to a metal silicide.

### Claim 4 (depends on 3)

The process of claim 3, wherein the metal silicide comprises a silicide of titanium or a silicide of nickel.

### Claim 5 (depends on 3)

The process of claim 3, wherein the metallic layer comprises titanium and wherein the annealing is carried out in excess of 550° C. for between 1 second and 24 hours.

### Claim 6 (depends on 3)

The process of claim 3, wherein the metallic layer comprises titanium, and wherein the annealing is carried out (a) at 550° C. to 600° C. for 12-24 hours; (b) at 600° C. to 750° C. for 5 minutes to 12 hours; (c) at 750° C. to 800° C. for 1 minute to 5 minutes, or (d) at 800° C. to 1000° C. for 1 second to 1 minute.

### Claim 7 (depends on 3)

The process of claim 3, wherein the metallic layer comprises nickel, wherein the annealing is carried out between about 350° C. to about 450° C.

### Claim 8 (depends on 3)

The process of claim 3, further comprising forming contacts through the passivation layer to the metal silicide, the third conductive layer and the first conductive layer.