# US 11,910,610 B2 · Semiconductor device, memory device, and method for forming transistor on substrate

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- Number: US 11,910,610 B2
- Document ID: US11910610B2
- Status: Granted
- Kind: B2
- Application number: 17/191,249
- Filed: 2021-03-03
- Published: 2022-03-24
- Granted: 2024-02-20
- Earliest claimed: 2020-09-18
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Tatsuya Hosoda; Yasuhisa Naruta
- Web page: https://patentgrep.com/patent/US11910610B2

## CPC

- H10B 43/40: characterised by the peripheral circuit region
- H10D 64/01312: {the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 64/01306: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon}
- H10D 64/662: {the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a substrate, a gate insulating layer on the substrate, and a stacked semiconductor layer. The stacked semiconductor layer includes a first layer formed on the gate insulating layer and including a phosphorus-doped polycrystalline semiconductor, a second layer formed on the first layer and including a carbon-doped polycrystalline semiconductor, and a third layer formed on the second layer and including a phosphorus-doped or undoped polycrystalline semiconductor. The semiconductor device further includes a metal layer on or above the stacked semiconductor layer. The third layer includes less phosphorus than the first layer or does not include phosphorus.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a gate insulating layer on the substrate;
a stacked semiconductor layer including:
a first layer formed on the gate insulating layer and including a phosphorus-doped polycrystalline semiconductor,
a second layer formed on the first layer and including a carbon-doped polycrystalline semiconductor, and
a third layer formed on the second layer and including a phosphorus-doped or undoped polycrystalline semiconductor; and
a metal layer on or above the stacked semiconductor layer, wherein
the third layer includes less phosphorus than the first layer or does not include phosphorus.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising:
an oxide layer between the third layer and the metal layer.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the metal layer is a stacked body including a tungsten silicide layer and a titanium nitride layer that are stacked in this order from the stacked semiconductor layer.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the metal layer is formed on the third layer and is a stacked body including a titanium layer, a titanium nitride layer, and a tungsten layer that are stacked in this order from the stacked semiconductor layer.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, further comprising:
an NMOS (N-type Metal Oxide Semiconductor) transistor and a PMOS (P-type Metal Oxide Semiconductor) transistor, wherein
the substrate includes a P-type well region and an N-type well region,
the NMOS transistor including the gate insulating layer, the stacked semiconductor layer, and the metal layer, is formed on the P-type well region, and
the PMOS transistor is formed on the N-type well region.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein
the P-type well region includes first and second N-type diffusion layers separated from each other along a surface of the substrate, and
the gate insulating layer is formed on the surface between the first and second N-type diffusion layers.

### Claim 7 (depends on 5)

The semiconductor device according to claim 5, wherein the substrate includes an isolation region that electrically separates the P-type well region from the N-type well region.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein a side surface of each of the gate insulating layer, the stacked semiconductor layer, and the metal layer, is covered by an insulating layer.

### Claim 9

A memory device, comprising:
one or more memory cell transistors; and
a peripheral circuit configured to control the memory cell transistors and including an NMOS (N-type Metal Oxide Semiconductor) transistor comprising:
a gate insulating layer formed on a substrate,
a stacked semiconductor layer including:
a first layer formed on the gate insulating layer and including a phosphorus doped polycrystalline semiconductor,
a second layer formed on the first layer and including a carbon-doped polycrystalline semiconductor, and
a third layer formed on the second layer and including a phosphorus-doped or undoped polycrystalline semiconductor, and
a metal layer on or above the stacked semiconductor layer, wherein the third layer includes less phosphorus than the first layer or does not include phosphorus.

### Claim 10 (depends on 9)

The memory device according to claim 9, wherein
the peripheral circuit further includes a PMOS (P-type Metal Oxide Semiconductor) transistor, and
the substrate includes a P-type well region on which the NMOS (N-type Metal Oxide Semiconductor) transistor is formed, and an N-type well region on which the PMOS transistor is formed.

### Claim 11 (depends on 10)

The memory device according to claim 10, wherein the P-type and N-type well regions are electrically separated from each other by an isolation region.

### Claim 12 (depends on 11)

The memory device according to claim 11, wherein the NMOS and PMOS transistors are adjacent to each other across the isolation region.

### Claim 13 (depends on 9)

The memory device according to claim 9, wherein
the P-type well region includes first and second N-type diffusion layers separated from each other along a surface of the substrate, and
the gate insulating layer is located on the surface between the first and second N-type diffusion layers.

### Claim 14 (depends on 9)

The memory device according to claim 9, further comprising:
a wiring extending along a direction parallel to the substrate and electrically connected to one or more of the memory cell transistors, wherein
the NMOS and PMOS transistors are arranged along the first direction.

### Claim 15 (depends on 9)

The memory device according to claim 9, further comprising:
a memory pillar extending along a direction in which the first, second, and third layers are stacked, and is used as a part of the memory cell transistors.

### Claim 16

A method for forming a transistor on a substrate, the method comprising:
forming a gate insulating layer on the substrate;
forming a stacked semiconductor layer that includes:
a first layer including a phosphorus-doped polycrystalline semiconductor on the gate insulating layer,
a second layer including a carbon-doped polycrystalline semiconductor on the first layer, and
a third layer including a phosphorus-doped or undoped polycrystalline semiconductor on the second layer, wherein the third layer includes less phosphorus than the first layer or does not include phosphorus; and
forming a metal layer on or above the third layer.

### Claim 17 (depends on 16)

The method according to claim 16, further comprising:
applying an oxide film to the third layer after the stacked semiconductor is formed but before the metal layer is formed;
forming a groove so as to penetrate the gate insulating layer, the stacked semiconductor layer, and the oxide film; and
removing the oxide film.

### Claim 18 (depends on 17)

The method according to claim 17, wherein
the substrate includes a P-type well region and an N-type well region, and
the method further comprises:
after the oxide film is applied, removing all of the layers formed on or above the N-type well region; and
before the metal layer are formed, applying another gate insulating layer and a polysilicon layer on the N-type well region.

### Claim 19 (depends on 16)

The method according to claim 16, wherein the metal layer is formed directly on the third layer and is a stacked body including a titanium layer, a titanium nitride layer, and a tungsten layer that are arranged in this order from the stacked semiconductor layer.

### Claim 20 (depends on 16)

The method according to claim 16, further comprising:
forming an oxide layer on the third layer before the metal layer is formed, wherein
the metal layer has a stacked body including a tungsten silicide layer and a titanium nitride layer that are arranged in this order from the stacked semiconductor layer.