# US 11,910,608 B2 · Semiconductor device and method for manufacturing same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,910,608 B2 - Document ID: US11910608B2 - Status: Granted - Kind: B2 - Application number: 17/961,950 - Filed: 2022-10-07 - Published: 2023-01-26 - Granted: 2024-02-20 - Earliest claimed: 2017-02-28 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Shinya Arai - Web page: https://patentgrep.com/patent/US11910608B2 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/40: characterised by the peripheral circuit region - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10W 10/021: {of air gaps} - H10W 10/20: Air gaps - G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND - H10D 62/834: further characterised by the dopants - H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz} - H10P 32/1414: {the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon} - H10P 32/171: {being group IV material} - H10P 50/264: {by chemical means} - H10P 50/283: {by chemical means} - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer. ## Claims ### Claim 1 A semiconductor device, comprising: a first semiconductor layer; a second semiconductor layer provided on and above the first semiconductor layer; a third semiconductor layer provided on and above the second semiconductor layer; a stacked body provided above the third semiconductor layer, the stacked body including a plurality of electrode layers stacked in a first direction; and a columnar portion including a fourth semiconductor layer and a first charge storage film, the fourth semiconductor layer extending through the stacked body, the third semiconductor layer and the second semiconductor layer, and reaches the first semiconductor layer in the first direction, and including a side wall portion in contact with the second semiconductor layer; a conductive layer extending through the stacked body and the third semiconductor layer in the first direction, extending in a second direction crossing the first direction, and having a first surface and a second surface opposing to the first surface in a third direction crossing the first direction and the second direction; a first insulating layer provided on the first surface of the conductive layer, and between the first surface and the stacked body; a second insulating layer provided on the second surface of the conductive layer, and between the second surface and the stacked body, wherein a lower end of the conductive layer protrudes lower than a lower end of the first insulating layer and a lower end of the second insulating layer. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the lower end of the conductive layer is in contact with the second semiconductor layer. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the first charge storage film is provided between the stacked body and the fourth semiconductor layer. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the side wall portion of the fourth semiconductor layer is not covered with the first charge storage film. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the second semiconductor layer includes an impurity. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, further comprising a gate layer provided between the third semiconductor layer and the stacked body, the gate layer being thicker than a thickness of one layer of the plurality of electrode layers. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein a distance between the side wall portion and a portion of the fourth semiconductor layer opposing the gate layer is less than a thickness of the gate layer. ### Claim 8 (depends on 6) The semiconductor device according to claim 6, wherein an impurity concentration of a first portion of the fourth semiconductor layer opposing the gate layer is higher than an impurity concentration of a second portion of the fourth semiconductor layer opposing the stacked body. ### Claim 9 (depends on 6) The semiconductor device according to claim 6, wherein at least one of the plurality of electrode layers is a first selection gate, at least one of the plurality of electrode layers except for the first selection gate is a second selection gate, plurality of the plurality of electrode layers except for the first selection gate and the second selection gate are a plurality of cell gates, the first selection gate is thinner than the gate layer; the second selection gate is provided between the first selection gate and the gate layer and is thinner than the gate layer; and a plurality of cell gates oppose the first charge storage film and is provided between the first selection gate and the second selection gate, and the plurality of cell gates each are thinner than the gate layer. ### Claim 10 (depends on 6) The semiconductor device according to claim 6, wherein the gate layer is a silicon layer including phosphorus. ### Claim 11 (depends on 6) The semiconductor device according to claim 6, wherein the first charge storage film is provided between the gate layer and the fourth semiconductor layer. ### Claim 12 (depends on 6) The semiconductor device according to claim 6, wherein the device is configured to apply a potential to the gate layer in an erase operation so that holes occur in a portion of the fourth semiconductor layer opposing the gate layer. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein an impurity concentration of the side wall portion of the fourth semiconductor layer is higher than an impurity concentration of a portion of the fourth semiconductor layer opposing the stacked body. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein the first semiconductor layer is a silicon layer including phosphorus. ### Claim 15 (depends on 1) The semiconductor device according to claim 1, wherein the second semiconductor layer is a silicon layer including phosphorus. ### Claim 16 (depends on 1) The semiconductor device according to claim 1, wherein the third semiconductor layer is a silicon layer including phosphorus. ### Claim 17 (depends on 1) The semiconductor device according to claim 1, further comprising a substrate, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer being provided between the substrate and the stacked body layer, the first semiconductor layer contacting the substrate. ### Claim 18 (depends on 17) The semiconductor device according to claim 17, wherein the substrate includes an n-type semiconductor region contacting the first semiconductor layer, and a p-type semiconductor region, the n-type semiconductor region and the p-type semiconductor region forming a p-n junction. ### Claim 19 (depends on 1) The semiconductor device according to claim 1, wherein a thickness of the third semiconductor layer is thinner than a thickness of the first semiconductor layer and a thickness of the second semiconductor layer. ### Claim 20 (depends on 1) The semiconductor device according to claim 1, further comprising a second charge storage film provided between the first semiconductor layer and the fourth semiconductor layer.