# US 11,910,606 B2 · Integrated assemblies comprising conductive levels having two different metal-containing structures laterally adjacent one another, and methods of forming integrated assemblies

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- Number: US 11,910,606 B2
- Document ID: US11910606B2
- Status: Granted
- Kind: B2
- Application number: 17/692,041
- Filed: 2022-03-10
- Published: 2022-06-23
- Granted: 2024-02-20
- Earliest claimed: 2019-09-27
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: John D. Hopkins; Jordan D. Greenlee
- Web page: https://patentgrep.com/patent/US11910606B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/10: characterised by the top-view layout
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/283: {by chemical means}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/43: Layouts of interconnections
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include first regions, and include second regions laterally adjacent to the first regions. The first regions have a first vertical thickness and at least two different metal-containing materials along the first vertical thickness. The second regions have a second vertical thickness at least as large as the first vertical thickness, and have only a single metal-containing material along the second vertical thickness. Dielectric-barrier material is laterally adjacent to the first regions. Charge-blocking material is laterally adjacent to the dielectric-barrier material. Charge-storage material is laterally adjacent to the charge-blocking material. Dielectric material is laterally adjacent to the charge storage material. Channel material is laterally adjacent to the dielectric material.

## Claims

### Claim 1

A method of forming an integrated assembly, comprising:
forming a vertical stack of alternating first and second levels; the first levels comprising first material and the second levels comprising second material;
forming an opening to extend through the stack;
forming channel material within the opening;
forming slits to extend through the stack, with the slits being laterally offset from the channel material;
after forming the slits, removing the second material to leave voids;
forming first conductive structures within the voids; the first conductive structures having proximal regions adjacent the channel material and having distal regions adjacent the slits;
removing the distal regions to form cavities adjacent the proximal regions;
forming second conductive structures within the cavities and directly against the proximal regions of the first conductive structures; and
forming a high-k dielectric material along upper and lower surfaces of the proximal regions of the first conductive structures, the high-k material being absent from upper and lower surfaces of the second conductive structures, the second conductive structure having a vertical thickness equal to a combined thickness of the first conductive structure and the high-k dielectric material along the upper and lower surfaces of the first conductive structure.

### Claim 2 (depends on 1)

The method of claim 1 wherein each of the first conductive structures comprises a conductive liner and a conductive core material; with the conductive liner being along an outer peripheral surface of the conductive core material.

### Claim 3 (depends on 1)

The method of claim 1 wherein dielectric-barrier material is formed within the voids to narrow the voids prior to the forming of the first conductive structures within the voids; and wherein the forming of the cavities comprises recessing the dielectric barrier material.

### Claim 4 (depends on 1)

The method of claim 1 further comprising forming charge-blocking material, charge-storage material and dielectric material within the opening and adjacent to the channel material.

### Claim 5

A method of forming an integrated assembly, comprising:
forming a vertical stack of alternating first and second levels; the first levels comprising first material and the second levels comprising second material;
forming an opening to extend through the stack;
forming channel material within the opening;
forming slits to extend through the stack, with the slits being laterally offset from the channel material;
after forming the slits, removing the second material to leave voids;
forming first conductive structures within the voids; the first conductive structures having proximal regions adjacent the channel material and having distal regions adjacent the slits;
removing the distal regions to form cavities adjacent the proximal regions; and
forming second conductive structures within the cavities and directly against the proximal regions of the first conductive structures; wherein the forming of the second conductive structures comprises:
forming semiconductor material within the cavities; and
replacing at least some of the semiconductor material with metal-containing material.

### Claim 6 (depends on 5)

The method of claim 5 wherein the semiconductor material is doped with one or both of carbon and boron.

### Claim 7 (depends on 5)

The method of claim 5 wherein the replacing comprises exposure of the semiconductor material to a precursor comprising a metal halide.

### Claim 8 (depends on 7)

The method of claim 7 wherein the metal halide is a metal fluoride.

### Claim 9 (depends on 5)

The method of claim 5 wherein the metal-containing material comprises one or more of cobalt, molybdenum, nickel, ruthenium, tantalum, titanium and tungsten.

### Claim 10 (depends on 9)

The method of claim 9 wherein the semiconductor material comprises one or both of germanium and silicon; and wherein only some of the semiconductor material is replaced with the metal-containing material while portions of the semiconductor material directly adjacent to the proximal regions of the first conductive structures are converted to one or both of metal silicide and metal germanide.

### Claim 11

A method of forming an integrated assembly, comprising:
forming conductive levels that alternate with insulative levels to form a stack; the forming the conductive levels comprising:
forming first regions of the conductive levels by forming a conductive core material and forming a conductive liner material along upper and lower surfaces of the conductive core material; the conductive liner material being compositionally different from the conductive core material; and
forming second regions of the conductive levels laterally adjacent the first regions, the second regions comprising a conductive rail having at least two portions laterally offset relative to one another, with one of the at least two portions having a first uniform composition along its total vertical thickness, and with another of the at least two portions having a second uniform composition, different from the first uniform composition, along its total vertical thickness.

### Claim 12 (depends on 11)

The method of claim 11 further comprising forming channel material passing through the vertical stack.

### Claim 13 (depends on 12)

The method of claim 12 further comprising forming memory cells which individually include segments of the first regions and segments of the channel material.

### Claim 14 (depends on 13)

The method of claim 13 further comprising forming a charge-blocking material, a charge-storage material, and a dielectric material between the segments of the first regions and the segments of the channel material.

### Claim 15 (depends on 11)

The method of claim 11 wherein the conductive rails of the second regions are formed directly against the conductive core material and the conductive liner material of the first regions.

### Claim 16 (depends on 11)

The method of claim 11 wherein interfaces between the first regions of the conductive levels and the second regions of the conductive levels are substantially straight vertical interfaces extending along the conductive liner material and the conductive core material.

### Claim 17 (depends on 11)

The method of claim 11 wherein interfaces between the first regions of the conductive levels and the second regions of the conductive levels include first vertical surfaces extending along the conductive core material and second vertical surfaces extending along the conductive liner material; and wherein the second vertical surfaces are horizontally offset relative to the first vertical surfaces.