# US 11,910,603 B2 · Semiconductor device and electronic system including the same

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- Number: US 11,910,603 B2
- Document ID: US11910603B2
- Status: Granted
- Kind: B2
- Application number: 17/225,493
- Filed: 2021-04-08
- Published: 2022-03-17
- Granted: 2024-02-20
- Earliest claimed: 2020-09-14
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jesuk Moon; Juyoung Lim; Jongsoo Kim; Sunil Shim; Haemin Lee; Wonseok Cho
- Web page: https://patentgrep.com/patent/US11910603B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/40: characterised by the peripheral circuit region
- H10B 43/10: characterised by the top-view layout
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A vertical memory device includes a gate electrode structure on a substrate, a channel extending through the gate electrode structure, and an etch stop layer on a sidewall of the gate electrode structure. The gate electrode structure includes gate electrodes spaced apart from each other in a first direction and stacked in a staircase shape. The channel includes a first portion and a second portion contacting the first portion. A lower surface of the second portion has a width less than a width of an upper surface of the first portion. The etch stop layer contacts at least one gate electrode of the gate electrodes, and overlaps an upper portion of the first portion of the channel in a horizontal direction. The at least one gate electrode contacting the etch stop layer is a dummy gate electrode including an insulating material.

## Claims

### Claim 1

A semiconductor device, comprising:
a gate electrode structure on a substrate, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate and stacked in a staircase shape;
a channel extending through the gate electrode structure, the channel including:
a first portion extending in the first direction on the substrate; and
a second portion extending in the first direction on and contacting the first portion, a lower surface of the second portion having a width less than a width of an upper surface of the first portion; and
an etch stop layer on a sidewall of the gate electrode structure and contacting at least one gate electrode of the gate electrodes, the etch stop layer overlapping an upper portion of the first portion of the channel in a horizontal direction parallel to the upper surface of the substrate,
wherein the at least one gate electrode contacting the etch stop layer is a dummy gate electrode including an insulating material.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the dummy gate electrode includes a nitride, and the etch stop layer includes an oxide.

### Claim 3 (depends on 1)

The semiconductor device as claimed in claim 1, wherein no electrical signals are applied to one of the gate electrodes that is disposed at a level directly above or directly below the dummy gate electrode.

### Claim 4 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising contact plugs electrically connected to respective ones of the gate electrodes except for the dummy gate electrode.

### Claim 5 (depends on 4)

The semiconductor device as claimed in claim 4, further comprising upper wirings electrically connected to the contact plugs and applying electrical signals thereto,
wherein the upper wirings are not electrically connected to one of the gate electrodes that is disposed at a level directly above or directly below the dummy gate electrode.

### Claim 6 (depends on 1)

The semiconductor device as claimed in claim 1, wherein each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate, and end portions in the second direction of the gate electrodes are disposed to form steps arranged in the second direction.

### Claim 7 (depends on 6)

The semiconductor device as claimed in claim 6, wherein the etch stop layer extends in the second direction, and an end portion of the etch stop layer in the second direction is aligned with an end portion in the second direction of the dummy gate electrode in a plan view.

### Claim 8 (depends on 1)

The semiconductor device as claimed in claim 1, wherein a width of the first portion of the channel except for an upper portion of the channel increases by a first increase rate from a bottom toward a top of the channel, and a width of the upper portion of the channel increases by a second increase rate greater than the first increase rate from a bottom toward a top of the channel.

### Claim 9 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first portion of the channel has a cup-like shape, and the second portion of the channel has a cylindrical shape connected to the first portion.

### Claim 10 (depends on 9)

The semiconductor device as claimed in claim 9, further comprising:
a charge storage structure covering an outer sidewall of the channel;
a filling pattern contacting an inner sidewall of the channel and having a pillar shape; and
a pad on upper surfaces of the channel and the filling pattern, the pad contacting an inner sidewall of the charge storage structure.

### Claim 11

A semiconductor device, comprising:
a gate electrode structure on a substrate, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate and stacked in a staircase shape;
a memory channel structure extending through the gate electrode structure, the memory channel structure including:
a channel including:
a first portion extending in the first direction on the substrate; and
a second portion extending in the first direction on and contacting the first portion, a lower surface of the second portion having a width less than a width of an upper surface of the first portion;
a charge storage structure on an outer sidewall of the channel;
a filling pattern contacting an inner sidewall of the channel and having a pillar shape; and
a pad on upper surfaces of the channel and the filling pattern, the pad contacting an inner sidewall of the charge storage structure;
an etch stop layer on a sidewall of the gate electrode structure and contacting a dummy gate electrode of the gate electrodes, the dummy gate electrode including an insulating material, and the etch stop layer overlapping an upper portion of the first portion of the channel in a horizontal direction parallel to the upper surface of the substrate;
contact plugs electrically connected to respective ones of the gate electrodes except for the dummy gate electrode; and
first upper wirings electrically connected to the contact plugs and applying electrical signals thereto.

### Claim 12 (depends on 11)

The semiconductor device as claimed in claim 11, wherein the dummy gate electrode is one of a plurality of dummy gate electrodes at a plurality of levels, respectively.

### Claim 13 (depends on 11)

The semiconductor device as claimed in claim 11, wherein the dummy gate electrode includes a nitride, and the etch stop layer includes an oxide.

### Claim 14 (depends on 11)

The semiconductor device as claimed in claim 11, wherein the first upper wirings are not electrically connected to one of the gate electrodes that is disposed at a level directly above or directly below the dummy gate electrode.

### Claim 15 (depends on 11)

The semiconductor device as claimed in claim 11, wherein each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate, and end portions in the second direction of the gate electrodes are disposed to form steps arranged in the second direction.

### Claim 16 (depends on 15)

The semiconductor device as claimed in claim 15, wherein the etch stop layer extends in the second direction, and an end portion of the etch stop layer in the second direction is aligned with an end portion in the second direction of the dummy gate electrode in a plan view.

### Claim 17 (depends on 11)

The semiconductor device as claimed in claim 11, wherein the first portion of the channel has a cup-like shape, and the second portion of the channel has a cylindrical shape connected to the first portion.

### Claim 18 (depends on 11)

The semiconductor device as claimed in claim 11, further comprising:
lower wirings under the substrate;
a through via extending through the substrate in the first direction, the through via being electrically connected to one of the lower wirings; and
a second upper wiring on the through via, the second upper wiring being electrically connected thereto.

### Claim 19

An electronic system, comprising:
a controller; and
a semiconductor device electrically connected to the controller through an input/output pad, the semiconductor device including:
peripheral circuit wirings electrically connected to the input/output pad; and
a memory cell structure electrically connected to the peripheral circuit wirings, the memory cell structure including:
a gate electrode structure on a substrate, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate and stacked in a staircase shape;
a channel extending through the gate electrode structure, the channel including:
a first portion extending in the first direction on the substrate; and
a second portion extending in the first direction on and contacting the first portion, a lower surface of the second portion having a width less than a width of an upper surface of the first portion;
a charge storage structure on an outer sidewall of the channel; and
an etch stop layer on a sidewall of the gate electrode structure and contacting a dummy gate electrode of the gate electrodes, the dummy gate electrode including an insulating material, and the etch stop layer overlapping an upper portion of the first portion of the channel in a horizontal direction parallel to the upper surface of the substrate.

### Claim 20 (depends on 19)

The electronic system as claimed in claim 19, further comprising:
a filling pattern contacting an inner sidewall of the channel and having a pillar shape;
a pad on upper surfaces of the channel and the filling pattern and contacting an inner sidewall of the charge storage structure;
contact plugs electrically connected to respective ones of the gate electrodes among the gate electrodes except for the dummy gate electrode; and
upper wirings electrically connected to the contact plugs and applying electrical signals thereto.