# US 11,910,602 B2 · Stacked connections in 3D memory and methods of making the same

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- Number: US 11,910,602 B2
- Document ID: US11910602B2
- Status: Granted
- Kind: B2
- Application number: 17/144,562
- Filed: 2021-01-08
- Published: 2021-05-06
- Granted: 2024-02-20
- Earliest claimed: 2018-08-14
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Jun Liu; Zongliang Huo
- Web page: https://patentgrep.com/patent/US11910602B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3456: {Polycrystalline}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10P 32/14: within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P 32/171: {being group IV material}
- H10P 50/283: {by chemical means}
- H10P 50/642: {Chemical etching}
- H10D 64/037: {comprising charge-trapping insulators}
- H10P 52/403: {of conductive or resistive materials}
- H10P 95/062: {involving a dielectric removal step}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.

## Claims

### Claim 1

A memory device, comprising:
a first layer stack having first alternating conductor and insulator layers;
a top dielectric layer disposed on the first layer stack;
a second layer stack, disposed over the top dielectric layer and having second alternating conductor and insulator layers;
a first vertical structure extending through the first layer stack, wherein the first vertical structure comprises a first NAND string having a first memory layer;
a second vertical structure extending through the second layer stack and at least a portion of the top dielectric layer, wherein the second vertical structure comprises a second NAND string having a second memory layer; and
a conductive material sandwiched between the first vertical structure and the second vertical structure, wherein:
the first memory layer comprises a first blocking layer, a first storage layer, a first tunneling layer and a first channel layer, wherein the first blocking layer, the first storage layer, the first tunneling layer and the first channel layer extend through the first layer stack;
the second memory layer comprises a second blocking layer, a second storage layer, a second tunneling layer and a second channel layer, wherein the second blocking layer, the second storage layer, the second tunneling layer and the second channel layer extend through the second layer stack;
a width of the conductive material is greater than a width of the first vertical structure and a width of the second vertical structure at interfaces contacting the conductive material; and
a portion of the conductive material surrounds a bottom portion of the second vertical structure, wherein the portion of the conductive material that surrounds the bottom portion of the second vertical structure is in direct contact with the second layer stack and is coplanar with the top dielectric layer.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein dopants originating from the conductive material are present in portions of the first channel layer and the second channel layer adjacent to the conductive material.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the conductive material is disposed over a recess on a top portion of the first NAND string and is in contact with the first blocking layer, the first storage layer, the first tunneling layer, and the first channel layer of the first NAND string.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the second NAND string further comprises a nested recess over the conductive material, the nested recess extending through the second blocking layer, the second storage layer and the second tunneling layer.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the second channel layer of the second NAND string is disposed over the nested recess, forming an ohmic contact with the conductive material.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the second vertical structure further comprises a top conductive material in a top portion, the top conductive material electrically connected to the second channel layer of the second NAND string.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the top conductive material comprises polysilicon.

### Claim 8 (depends on 6)

The memory device of claim 6, wherein dopants originating from the top conductive material are present in portions of the second channel layer adjacent to the top conductive material.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the conductive material projects outward from the first vertical structure and the second vertical structure.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the second vertical structure extends through a portion of the conductive material.

### Claim 11 (depends on 1)

The memory device of claim 1, wherein the top dielectric layer surrounds the conductive material.

### Claim 12 (depends on 1)

The memory device of claim 1, wherein the conductive material is configured to provide electrical connection between the first vertical structure and the second vertical structure.

### Claim 13 (depends on 1)

The memory device of claim 1, wherein the conductive material comprises polysilicon.

### Claim 14 (depends on 1)

The memory device of claim 1, further comprising:
a first staircase structure formed in the first layer stack; and
a second staircase structure formed in the second layer stack.

### Claim 15 (depends on 14)

The memory device of claim 14, further comprising:
a further first vertical structure extending through the first staircase structure; and
a further second vertical structure extending through the second staircase structure.

### Claim 16 (depends on 1)

The memory device of claim 1, wherein the portion of the conductive material that surrounds the bottom portion of the second vertical structure is in direct contact with a bottom insulator layer of the second alternating conductor and insulator layers in the second layer stack.

### Claim 17 (depends on 1)

The memory device of claim 1, wherein the portion of the conductive material that surrounds the bottom portion of the second vertical structure surrounds a bottom portion of the second blocking layer of the second NAND string.