# US 11,910,599 B2 · Contact structures for three-dimensional memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,910,599 B2 - Document ID: US11910599B2 - Status: Granted - Kind: B2 - Application number: 17/993,600 - Filed: 2022-11-23 - Published: 2023-03-23 - Granted: 2024-02-20 - Earliest claimed: 2018-12-12 - Assignees: Yangtze Memory Technologies Co., Ltd. - Applicants: Yangtze Memory Technologies Co., Ltd. - Inventors: Zhongwang Sun; Guangji Li; Kun Zhang; Ming Hu; Jiwei Cheng; Shijin Luo; Kun Bao; Zhiliang Xia - Web page: https://patentgrep.com/patent/US11910599B2 ## CPC - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/40: characterised by the peripheral circuit region - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring. ## Claims ### Claim 1 A memory device, comprising: a film stack, comprising a dielectric layer and a conductive layer alternatingly stacked in a first direction; a staircase structure disposed in the film stack and comprising a staircase step, wherein the staircase step comprises two or more alternatingly stacked dielectric layers and conductive layers; a barrier layer and a first insulating layer disposed on the staircase structure; and a coaxial contact structure disposed on the staircase step and extending through the first insulating layer and the barrier layer in the first direction, wherein: the coaxial contact structure comprises a conductive ring, an insulating ring and a conductive core, wherein the insulating ring is disposed between the conductive ring and the conductive core; a bottom surface of the conductive core contacts a lowermost conductive layer of the staircase step; a bottom surface of the conductive ring contacts an upper conductive layer stacked above the lowermost conductive layer; and a bottom surface of the insulating ring contacts a corresponding dielectric layer disposed between the lowermost conductive layer and the upper conductive layer of the staircase step. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the conductive core is in a center of the coaxial contact structure and comprises a diameter smaller that a diameter of the conductive ring. ### Claim 3 (depends on 1) The memory device of claim 1, wherein in the first direction a length of the conductive core is longer than a length of the conductive ring. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the insulating ring covers an outer sidewall of the conductive core and an inner sidewall of the conductive ring. ### Claim 5 (depends on 4) The memory device of claim 4, wherein at least a portion of a sidewall of the insulating ring contacts a sidewall of the upper conductive layer. ### Claim 6 (depends on 1) The memory device of claim 1, wherein in the first direction a length of the conductive core is longer than a length of the insulating ring. ### Claim 7 (depends on 1) The memory device of claim 1, wherein at least a portion of a sidewall of the conductive ring contacts a sidewall of the barrier layer. ### Claim 8 (depends on 1) The memory device of claim 1, further comprising memory strings extending through the film stack in the first direction. ### Claim 9 (depends on 1) The memory device of claim 1, wherein the coaxial contact structure is coplanar with the first insulating layer at an end further way from the staircase step. ### Claim 10 A memory device, comprising: a staircase step comprising alternatingly stacked dielectric layers and conductive layers; a barrier layer disposed on the staircase step and covering a sidewall and a top surface of the staircase step; a first insulating layer disposed on the barrier layer; a coaxial contact structure extending through the first insulating layer and the barrier layer and configured to provide electrical connections for the conductive layers of the staircase step, wherein: the coaxial contact structure comprises an outer conductive ring, an insulating ring and an inner conductive ring, wherein the insulating ring is disposed between the outer conductive ring and the inner conductive ring; a bottom surface of the outer conductive ring and a bottom surface of the inner conductive ring contact an upper conductive layer and a lower conductive layer of the staircase step, respectively; and a bottom surface of the insulating ring contacts a corresponding dielectric layer disposed between the upper conductive layer and the lower conductive layer of the staircase step. ### Claim 11 (depends on 10) The memory device of claim 10, wherein a diameter of the outer conductive ring is larger than a diameter of the inner conductive ring. ### Claim 12 (depends on 10) The memory device of claim 10, wherein a length of the outer conductive ring is shorter than a length of the inner conductive ring. ### Claim 13 (depends on 10) The memory device of claim 10, wherein the insulating ring is configured to isolate the outer conductive ring and the inner conductive ring. ### Claim 14 (depends on 13) The memory device of claim 13, wherein at least a portion of a sidewall of the insulating ring contacts a sidewall of the upper conductive layer.