# US 11,910,592 B2 · Capacitor and a DRAM device including the same

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- Number: US 11,910,592 B2
- Document ID: US11910592B2
- Status: Granted
- Kind: B2
- Application number: 17/702,190
- Filed: 2022-03-23
- Published: 2023-01-05
- Granted: 2024-02-20
- Earliest claimed: 2021-07-02
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Kyooho Jung; Dongkwan Baek; Cheoljin Cho
- Web page: https://patentgrep.com/patent/US11910592B2

## CPC

- H10B 12/315: {with the capacitor higher than a bit line}
- H10D 1/716: {having vertical extensions}
- H10B 12/033: {the capacitor extending over the transistor}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10D 1/68: Capacitors having no potential barriers
- H10D 1/684: {the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A capacitor may include a lower electrode, a dielectric layer structure on the lower electrode, and an upper electrode on the dielectric layer structure. The dielectric layer structure may include a plurality of dielectric layers and at least one insert layer structure between ones of the plurality of dielectric layers. The insert layer structure may include a plurality of zirconium oxide layers and at least one insert layer. The insert layer may be between ones of the plurality of zirconium oxide layers. The capacitor may have a high capacitance and low leakage currents.

## Claims

### Claim 1

A capacitor, comprising:
a lower electrode;
a dielectric layer structure on the lower electrode, the dielectric layer structure comprising a plurality of dielectric layers and at least one insert layer structure between ones of the plurality of dielectric layers; and
an upper electrode on the dielectric layer structure,
wherein the at least one insert layer structure includes a plurality of zirconium oxide layers and at least two insert layers, and each of the at least two the insert layers is between ones of the plurality of zirconium oxide layers, wherein the insert layer structure comprising at least two insert layers is higher than a central portion in a vertical direction of the dielectric layer structure.

### Claim 2 (depends on 1)

The capacitor of claim 1, wherein the at least two insert layers comprises a material selected from Al2O3, MgO, BeO, Y2O3, La2O3, CaO, and SiO2.

### Claim 3 (depends on 1)

The capacitor of claim 1, wherein the dielectric layer structure has a thickness of 30 Å to 60 Å.

### Claim 4 (depends on 1)

The capacitor according to claim 1, wherein a thickness of each of the at least two insert layers is less than a thickness of each zirconium oxide layer.

### Claim 5 (depends on 1)

The capacitor of claim 1, wherein a sum of thicknesses of the at least two insert layers included in the dielectric layer structure is 1 Å to 3 Å.

### Claim 6 (depends on 1)

The capacitor of claim 1, wherein each of the plurality of dielectric layers comprises at least one material selected from HfO2, ZrO2, TiO2, TaO2, and La2O3.

### Claim 7 (depends on 1)

The capacitor of claim 1, wherein the dielectric layer structure further includes an upper interface layer between an uppermost dielectric layer and the upper electrode, and wherein the upper interface layer is a material selected from Al2O3, MgO, BeO, Y2O3, La2O3, CaO, and SiO2.

### Claim 8 (depends on 1)

The capacitor of claim 1, wherein each of the plurality of dielectric layers comprises a hafnium oxide layer, and wherein the insert layer structure comprises a first zirconium oxide layer, an aluminum oxide layer, and a second zirconium oxide layer stacked sequentially.

### Claim 9 (depends on 1)

The capacitor of claim 1, wherein the plurality of zirconium oxide layers directly contacts the at least two insert layers.

### Claim 10

A capacitor, comprising:
a lower electrode;
a dielectric layer structure on the lower electrode, the dielectric layer structure including a plurality of dielectric layers and a single insert layer structure between ones of the plurality of dielectric layers; and
an upper electrode on the dielectric layer structure;
wherein the single insert layer structure includes at least a first zirconium oxide layer, an aluminum oxide layer, and a second zirconium oxide layer stacked sequentially,
wherein the dielectric layer structure includes a plurality of aluminum oxide layers,
wherein the single insert layer structure includes the plurality of aluminum oxide layers spaced apart from each other and the single insert layer structure comprising the plurality of aluminum oxide layers is higher than a central portion in a vertical direction of the dielectric layer structure, and
wherein a thickness of each of the plurality of aluminum oxide layers is less than a thickness of the first zirconium oxide layer and the second zirconium oxide layer and a sum of thicknesses of the aluminum oxide layers in the dielectric layer structure is 1 Å to 3 Å.

### Claim 11 (depends on 10)

The capacitor of claim 10, wherein each of the plurality of dielectric layers include at least one material selected from HfO2, ZrO2, TiO2, TaO2, and La2O3.

### Claim 12 (depends on 10)

The capacitor of claim 10, wherein the dielectric layer structure further includes an upper interface layer between an uppermost dielectric layer and the upper electrode.

### Claim 13 (depends on 10)

The capacitor of claim 10, wherein the first zirconium oxide layer and the second zirconium oxide layer directly contact the aluminum oxide layer.

### Claim 14

A DRAM device, comprising:
a cell transistor on a substrate, the cell transistor including a gate structure, a first impurity region, and a second impurity region;
a bit line structure electrically connected to the first impurity region;
a capacitor on the bit line structure, the capacitor electrically connected to the second impurity region,
wherein the capacitor comprises:
a lower electrode;
a dielectric layer structure on the lower electrode, the dielectric layer structure including a plurality of dielectric layers and at least one insert layer structure between ones of the plurality of dielectric layers, the dielectric layer structure having a thickness of 30 Å to 60 Å; and
an upper electrode on the dielectric layer structure,
wherein the at least one insert layer structure comprises at least a first zirconium oxide layer, an aluminum oxide layer, and a second zirconium oxide layer stacked sequentially, and
wherein the dielectric layer structure includes a plurality of aluminum oxide layers,
wherein the at least one insert layer structure comprises a single insert layer structure in the dielectric layer structure, and wherein the single insert layer structure includes the plurality of aluminum oxide layers spaced apart from each other and the single insert layer structure comprising the plurality of aluminum oxide layers is higher than a central portion in a vertical direction of the dielectric layer structure.

### Claim 15 (depends on 14)

The DRAM device of claim 14, wherein a sum of thicknesses of aluminum oxide layers included in the insert layer structure is 1 Å to 3 Å.

### Claim 16 (depends on 14)

The DRAM device of claim 14, wherein the first zirconium oxide layer and the second zirconium oxide layer directly contact the aluminum oxide layer.