# US 11,910,591 B2 · Memory cell and semiconductor memory device with the same

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- Number: US 11,910,591 B2
- Document ID: US11910591B2
- Status: Granted
- Kind: B2
- Application number: 17/399,471
- Filed: 2021-08-11
- Published: 2022-08-25
- Granted: 2024-02-20
- Earliest claimed: 2021-02-22
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Seung Hwan Kim
- Web page: https://patentgrep.com/patent/US11910591B2

## CPC

- H10B 12/05: {Making the transistor}
- H10B 12/312: {with a bit line higher than the capacitor}
- H10B 12/482: {Bit lines}
- H10B 12/488: {Word lines}
- H10B 12/50: {Peripheral circuit region structures}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D 1/714: {having horizontal extensions}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention provides a highly integrated memory cell and a semiconductor memory device including the same. According to the present invention, a semiconductor memory device comprises: a memory cell array in which a plurality of memory cells is vertically stacked to a substrate, wherein each of the memory cells includes: a bit line vertically oriented to the substrate; a capacitor laterally spaced apart from the bit line; an active layer laterally oriented between the bit line and the capacitor; and a word line and a back gate facing each other with the active layer interposed therebetween, and wherein an edge of the word line and an edge of the back gate have a step shape along a stacking direction of the memory cells.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a memory cell array in which a plurality of memory cells is vertically stacked to a substrate,
wherein each of the memory cells includes:
a bit line vertically oriented to the substrate;
a capacitor laterally spaced apart from the bit line;
an active layer laterally oriented between the bit line and the capacitor; and
a word line and a back gate facing each other with the active layer interposed therebetween,
wherein an edge of the word line and an edge of the back gate form a step shape along a stacking direction of the memory cells.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, further including a word line contact plug and a back gate contact plug connected to the edge of the word line and the edge of the back gate having a step shape, respectively.

### Claim 3 (depends on 2)

The semiconductor memory device of claim 2, wherein the word line contact plug is disposed on an edge of one side of the memory cell array, and the back gate contact plug is disposed on an edge of another side of the memory cell array which is opposite to said one side.

### Claim 4 (depends on 1)

The semiconductor memory device of claim 1, wherein the active layer includes:
a first source/drain region connected to the bit line;
a second source/drain region connected to the capacitor; and
a channel between the first source/drain region and the second source/drain region,
wherein the channel is thinner than the second source/drain region.

### Claim 5 (depends on 4)

The semiconductor memory device of claim 4, wherein
the word line and the back gate face each other with the channel interposed therebetween,
the word line is disposed above the channel, and
the back gate is disposed below the channel.

### Claim 6 (depends on 4)

The semiconductor memory device of claim 4, wherein
the word line and the back gate face each other with the channel interposed therebetween,
the word line is disposed below the channel, and
the back gate is disposed above the channel.

### Claim 7 (depends on 4)

The semiconductor memory device of claim 4, wherein the channel has a thickness thinner than a thickness of each of the word line and the back gate.

### Claim 8 (depends on 4)

The semiconductor memory device of claim 4, wherein the channel has a thickness of 1 nm to 7 nm.

### Claim 9 (depends on 1)

The semiconductor memory device of claim 1, wherein the word line and the back gate include the same material.

### Claim 10 (depends on 1)

The semiconductor memory device of claim 1, wherein the active layer includes polysilicon, silicon-germanium, or indium gallium zinc oxide.

### Claim 11 (depends on 1)

The semiconductor memory device of claim 1, wherein the memory cell array includes a DRAM cell array.

### Claim 12 (depends on 1)

The semiconductor memory device of claim 1,
wherein the capacitor includes:
a storage node which is connected to the active layer and laterally oriented;
a dielectric layer on the storage node; and
a plate node on the dielectric layer, wherein the storage node has a cylinder shape.

### Claim 13 (depends on 1)

The semiconductor memory device of claim 1, wherein the substrate includes a peripheral circuit for controlling the memory cell array.

### Claim 14 (depends on 13)

The semiconductor memory device of claim 13, wherein the peripheral circuit includes a sub word line driver for controlling the word lines and a sub hole circuit for controlling the back gates.

### Claim 15 (depends on 14)

The semiconductor memory device of claim 14, wherein the sub word line driver and the memory cell array are vertically overlapped.

### Claim 16

A semiconductor memory device, comprising:
a memory cell array in which a plurality of memory cells is stacked vertical to a substrate,
wherein each of the memory cells includes:
a bit line vertically oriented to the substrate;
a capacitor laterally spaced apart from the bit line;
an active layer including a thin-body channel, the thin-body channel being laterally disposed between the bit line and the capacitor; and
a word line and a back gate facing each other with the thin-body channel interposed therebetween,
wherein an edge of the word line and an edge of the back gate form a step shape along a stacking direction of the memory cells.

### Claim 17 (depends on 16)

The semiconductor memory device of claim 16, further including a word line contact plug and a back gate contact plug connected to the edge of the word line and the edge of the back gate having a step shape, respectively.

### Claim 18 (depends on 17)

The semiconductor memory device of claim 17, wherein the word line contact plug is disposed on an edge of one side of the memory cell array, and the back gate contact plug is disposed on an edge of another side of the memory cell array which is opposite to said one side.

### Claim 19 (depends on 16)

The semiconductor memory device of claim 16, wherein the word line is disposed above the thin-body channel, and the back gate is disposed below the thin-body channel.

### Claim 20 (depends on 16)

The semiconductor memory device of claim 16, wherein the word line is disposed below the thin-body channel, and the back gate is disposed above the thin-body channel.

### Claim 21 (depends on 16)

The semiconductor memory device of claim 16, wherein the thin-body channel has a thickness thinner than a thickness of each of the word line and the back gate.

### Claim 22 (depends on 16)

The semiconductor memory device of claim 16, wherein the thin-body channel has a thickness of 1 nm to 7 nm.

### Claim 23 (depends on 16)

The semiconductor memory device of claim 16, wherein the thin-body channel includes polysilicon, silicon-germanium, or indium gallium zinc oxide.