# US 11,910,590 B2 · Memory cell and semiconductor memory device with the same

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- Number: US 11,910,590 B2
- Document ID: US11910590B2
- Status: Granted
- Kind: B2
- Application number: 17/368,376
- Filed: 2021-07-06
- Published: 2022-08-04
- Granted: 2024-02-20
- Earliest claimed: 2021-02-01
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Seung Hwan Kim
- Web page: https://patentgrep.com/patent/US11910590B2

## CPC

- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/488: {Word lines}
- H10B 12/50: {Peripheral circuit region structures}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention provides a highly integrated memory cell and a semiconductor memory device including the same. According to the present invention, a semiconductor memory device comprises: a substrate; an active layer spaced apart from the substrate, extending in a direction parallel to the substrate, and including a thin-body channel; a bit line extending in a direction vertical to the substrate and connected to one side of the active layer; a capacitor connected to another side of the active layer; and a first word line and a second word line extending in a direction crossing the thin-body channel with the thin-body channel interposed therebetween, wherein a thickness of the thin-body channel is smaller than thicknesses of the first word line and the second word line.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a substrate;
an active layer spaced apart from the substrate, extending in a direction parallel to the substrate, and including a thin-body channel;
a bit line extending in a direction vertical to the substrate and connected to one side of the active layer;
a capacitor connected to another side of the active layer;
a first word line and a second word line extending in a direction crossing the thin-body channel with the thin-body channel interposed therebetween,
a bit line contact node disposed between one side of the active layer and the bit line;
a bit line side-ohmic contact disposed between the bit line contact node and the bit line;
a storage contact node disposed between another side of the active layer and the capacitor; and
a storage node side-ohmic contact disposed between the storage contact node and the capacitor,
wherein a thickness of the thin-body channel is smaller than thicknesses of the first word line and the second word line.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein the active layer further includes a first source/drain region connected to the bit line and a second source/drain region connected to the capacitor, and
the first source/drain region and the second source/drain region are positioned at both sides of the thin-body channel.

### Claim 3 (depends on 2)

The semiconductor memory device of claim 2,
wherein the thickness of the thin-body channel is smaller than a thickness of each the first and second source/drain regions.

### Claim 4 (depends on 2)

The semiconductor memory device of claim 2, wherein
the thickness of the thin-body channel is smaller than that of the second source/drain region, and
the thickness of the thin-body channel is equal to that of the first source/drain region.

### Claim 5 (depends on 1)

The semiconductor memory device of claim 1, wherein the thin-body channel includes a semiconductor material or an oxide semiconductor material.

### Claim 6 (depends on 1)

The semiconductor memory device of claim 1, wherein the thin-body channel includes silicon, germanium, silicon-germanium, or indium gallium zinc oxide (IGZO).

### Claim 7 (depends on 1)

The semiconductor memory device of claim 1, further including a word line pad, the word line pad interconnecting the first word line and the second word line.

### Claim 8 (depends on 1)

The semiconductor memory device of claim 1, wherein edge portions of the first word line and the second word line have a step-shape along a direction vertical to the substrate.

### Claim 9 (depends on 1)

The semiconductor memory device of claim 1, wherein each of the bit line contact node and the storage contact node includes polysilicon.

### Claim 10 (depends on 1)

The semiconductor memory device of claim 1, wherein each of the bit line side-ohmic contact and the storage node side-ohmic contact includes metal silicide.

### Claim 11 (depends on 1)

The semiconductor memory device of claim 1, wherein the capacitor includes a cylinder-type storage node, the cylinder-type storage node being connected to the another side of the active layer.

### Claim 12

A semiconductor memory device, comprising:
a substrate;
an active layer spaced apart from the substrate, extending in a direction parallel to the substrate, and including a first source/drain region, a second source/drain region and a thin-body channel between the first source/drain region and the second source/drain region;
a bit line extending in a direction vertical to the substrate and connected to the first source/drain region;
a capacitor connected to the second source/drain region; and
a first word line and a second word line extending in a direction crossing the thin-body channel with the thin-body channel interposed therebetween,
wherein a thickness of the thin-body channel is smaller than thicknesses of the first word line and the second word line, wherein
the thickness of the thin-body channel is smaller than that of first source/drain region, and
the thickness of the thin-body channel is equal to that of the second source/drain region.

### Claim 13

A semiconductor memory device, comprising:
a substrate; and
a memory cell array including memory cells stacked along a direction vertical to the substrate,
wherein each of the memory cells comprises:
a bit line vertically oriented to the substrate;
a capacitor laterally spaced apart from the bit line;
an active layer laterally oriented between the bit line and the capacitor; and
a word line disposed on an upper portion of the active layer and laterally oriented to intersect with the active layer,
a bit line contact node disposed between one side of the active layer and the bit line;
a bit line side-ohmic contact disposed between the bit line contact node and the bit line;
a storage contact node disposed between another side of the active layer and the capacitor; and
a storage node side-ohmic contact disposed between the storage contact node and the capacitor,
wherein the active layer includes a thin-body channel, a thickness of the thin-body channel is smaller than a thickness of the word line.

### Claim 14 (depends on 13)

The semiconductor memory device of claim 13, wherein
the word line includes first and second word lines, the first and second word lines crossing the thin-body channel with the thin-body channel interposed therebetween, and
a thickness of the thin-body channel is smaller than thicknesses of the first word line and the second word line.

### Claim 15 (depends on 13)

The semiconductor memory device of claim 13, wherein the active layer further includes a first source/drain region connected to the bit line and a second source/drain region connected to the capacitor, and
the first source/drain region and the second source/drain region are positioned at both sides of the thin-body channel.

### Claim 16 (depends on 15)

The semiconductor memory device of claim 15,
wherein a thickness of the thin-body channel is smaller than a thickness of each of the first source/drain region and the second source/drain region.

### Claim 17 (depends on 15)

The semiconductor memory device of claim 15, wherein
a thickness of the thin-body channel is smaller than that of the second source/drain region, and
the thickness of the thin-body channel is equal to that of the first source/drain region.

### Claim 18 (depends on 13)

The semiconductor memory device of claim 13, wherein the thin-body channel includes a semiconductor material or an oxide semiconductor material.

### Claim 19 (depends on 13)

The semiconductor memory device of claim 13, wherein word lines of the memory cells have a step-shape along a direction vertical to a surface of the substrate.

### Claim 20 (depends on 13)

The semiconductor memory device of claim 13, wherein the memory cells include a dynamic random-access memory (DRAM) cell.

### Claim 21 (depends on 13)

The semiconductor memory device of claim 13, wherein the substrate includes a peripheral circuit for controlling the memory cell array.

### Claim 22 (depends on 21)

The semiconductor memory device of claim 21, wherein the peripheral circuit is disposed at a lower level or a higher level than the memory cell array.

### Claim 23

A semiconductor memory device, comprising:
a substrate; and
a memory cell array including memory cells stacked along a direction vertical to the substrate,
wherein each of the memory cells comprises:
a bit line vertically oriented to the substrate;
a capacitor laterally spaced apart from the bit line;
an active layer laterally oriented between the bit line and the capacitor, and including a first source/drain region, a second source/drain region and a thin-body channel between the first source/drain region and the second source/drain region;
a word line disposed on an upper portion of the active layer and laterally oriented to intersect with the active layer,
wherein a thickness of the thin-body channel is smaller than a thickness of the word line, wherein
a thickness of the thin-body channel is smaller than that of first source/drain region, and
the thickness of the thin-body channel is equal to that of the second source/drain region.