# US 11,910,589 B2 · Memory device comprising electrically floating body transistor

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- Number: US 11,910,589 B2
- Document ID: US11910589B2
- Status: Granted
- Kind: B2
- Application number: 17/333,540
- Filed: 2021-05-28
- Published: 2021-09-16
- Granted: 2024-02-20
- Earliest claimed: 2013-03-09
- Assignees: Zeno Semiconductor, Inc.
- Applicants: Zeno Semiconductor, Inc.
- Inventors: Jin-Woo Han; Yuniarto Widjaja
- Web page: https://patentgrep.com/patent/US11910589B2

## CPC

- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell
- G11C 11/407: for memory cells of the field-effect type
- G11C 16/00: Erasable programmable read-only memories (G11C14/00 takes precedence)
- G11C 16/0416: {comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM}
- H10B 43/35: with cell select transistors, e.g. NAND
- H10D 30/685: {from the channel}
- H10D 30/711: {having floating bodies}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.

## Claims

### Claim 1

An integrated circuit comprising:
a semiconductor memory array comprising a plurality of semiconductor memory cells, wherein each of said semiconductor memory cells comprises:
a memory transistor comprising:
a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
a first insulating region located above said floating body region;
second insulating regions adjacent to said floating body region; and
a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions;
wherein said floating body region is configured to be bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, and a depletion region formed as a result of an application of a back bias to said buried layer region; and
an access device comprising a body region, wherein said access device is connected in series to said memory transistor, and wherein said body region is configured to be isolated from said floating body region by said depletion region;
wherein said buried layer region is located underneath at least two of said memory cells; and
a control circuit configured to apply said back bias to said buried layer region.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, further comprising a substrate region, wherein said buried layer region is positioned between said substrate region and said floating body region.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein said back bias is applied as a constant positive voltage bias.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein said back bias is applied as a periodic pulse of positive voltage.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein said buried layer region is configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell.

### Claim 6

An integrated circuit comprising:
a semiconductor memory array comprising a plurality of semiconductor memory cells, wherein each of said semiconductor memory cells comprises:
a memory transistor comprising:
a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
a first insulating region located above said floating body region;
second insulating regions adjacent to said floating body region; and
a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions;
wherein said floating body region is configured to be bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, and a depletion region formed as a result of an application of a back bias to said buried layer region;
wherein application of said back bias results in at least two stable floating body charge levels;
an access device comprising a body region, wherein said access device is connected in series to said memory transistor, and wherein said body region is configured to be isolated from said floating body region by said depletion region;
wherein said buried layer region is located underneath at least two of said memory cells; and
a control circuit configured to apply said back bias to said buried layer region.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, further comprising a substrate region, wherein said buried layer region is positioned between said substrate region and said floating body region.

### Claim 8 (depends on 6)

The integrated circuit of claim 6, wherein said back bias is applied as a constant positive voltage bias.

### Claim 9 (depends on 6)

The integrated circuit of claim 6, wherein said back bias is applied as a periodic pulse of positive voltage.

### Claim 10 (depends on 6)

The integrated circuit of claim 6, wherein said buried layer region is configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell.

### Claim 11

An integrated circuit comprising:
a semiconductor memory array comprising a plurality of semiconductor memory cells, wherein each of said semiconductor memory cells comprises:
a memory transistor comprising:
a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
insulating regions adjacent to said floating body region;
a buried layer region located below said floating body region and said insulating regions and spaced from said insulating regions so as not to contact said insulating regions;
wherein said floating body region is configured to be bounded by said insulating regions and a depletion region formed as a result of an application of a back bias to said buried layer region;
wherein said buried layer region generates impact ionization when said memory cell is in one of said first and second states, and wherein said back-bias region does not generate impact ionization when the memory cell is in the other of said first and second states;
an access device comprising a body region, wherein said access device is connected in series to said memory transistor, and wherein said body region is configured to be isolated from said floating body region by said depletion region;
wherein said buried layer region is located underneath at least two of said memory cells; and
a control circuit configured to apply said back bias to said buried layer region.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, further comprising a substrate region, wherein said buried layer region is positioned between said substrate region and said floating body region.

### Claim 13 (depends on 11)

The integrated circuit of claim 11, wherein said back bias is applied as a constant positive voltage bias.

### Claim 14 (depends on 11)

The integrated circuit of claim 11, wherein said back bias is applied as a periodic pulse of positive voltage.

### Claim 15 (depends on 11)

The integrated circuit of claim 11, wherein said buried layer region is configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell.