# US 11,910,587 B2 · Memory circuit having SRAM memory cells and method for forming a SRAM memory cell structure

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- Number: US 11,910,587 B2
- Document ID: US11910587B2
- Status: Granted
- Kind: B2
- Application number: 17/410,860
- Filed: 2021-08-24
- Published: 2022-09-01
- Granted: 2024-02-20
- Earliest claimed: 2021-02-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hidehiro Fujiwara; Yi-Hsin Nien; Hung-Jen Liao
- Web page: https://patentgrep.com/patent/US11910587B2

## CPC

- H10B 10/18: {Peripheral circuit regions}
- H10D 89/10: Integrated device layouts
- G11C 11/412: using field-effect transistors only
- G11C 15/04: using semiconductor elements
- H10B 10/12: {comprising a MOSFET load element}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An apparatus includes memory cells. A first memory cell of the memory cells includes a first write port laid out in a first doping region and a first read port laid out in a second doping region. The first read port is separated from the first write port by a second write port of a second memory cell of the memory cells.

## Claims

### Claim 1

An apparatus comprising:
a plurality of memory cells including at least a first memory cell and a second memory cell;
a first write port comprising a plurality of first write access transistors formed within a first area and laid out in a first doping region of the first memory cell; and
a first read port comprising a plurality of first read access transistors formed within a second area and laid out in a second doping region of the first memory cell, the first read port being separated from the first write port by a second write port of the second memory cell,
wherein the second write port comprises a plurality of second write access transistors formed within a third area between the first area and the second area.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the first memory cell and the second memory cell are memory cells in adjacent rows of the same column.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the second memory cell comprises:
the second write port and a second read port laid out in the second doping region.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the second memory cell comprises:
the second write port laid out in the first doping region; and
a second read port laid out in the second doping region.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the first write port comprises n-type transistors, and the first doping region and the second doping region are n-plus (NP) regions.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the first write port comprises p-type transistors, the first doping region is a p-plus (PP) region, and the second doping region is an NP region.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the first memory cell further comprises another first read port laid out in the first doping region, and the second memory cell further comprises another second read port laid out in the first doping region.

### Claim 8

An apparatus, comprising:
a first memory cell and a second memory cell, the first memory cell comprising:
a first storage unit comprising n-type transistors formed in a first n-plus (NP) region and p-type transistors formed in a first p-plus (PP) region between the first NP region and a second NP region;
a plurality of first write access transistors formed in the first NP region or in the first PP region; and
a plurality of first read access transistors formed in the second NP region;
wherein a first write port is laid out in the first NP region of the first memory cell and a first read port laid out in the second NP region of the first memory cell, the first read port being separated from the first write port by a second write port of the second memory cell.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the second memory cell comprises:
a second storage unit comprising n-type transistors formed in the second NP region and p-type transistors formed in the first PP region;
a plurality of second write access transistors formed in the second NP region or in the first PP region; and
a plurality of second read access transistors formed in the second NP region.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein one of the first read access transistors is connected to a corresponding one of the second read access transistors by one or more conductive features in one or more conductive layers formed over the first read access transistors and the second read access transistors.

### Claim 11 (depends on 9)

The apparatus of claim 9, wherein one of the first write access transistors is connected to a corresponding one of the second write access transistors by one or more conductive features in one or more conductive layers formed over the first write access transistors and the second write access transistors.

### Claim 12 (depends on 9)

The apparatus of claim 9, wherein the second memory cell further comprises a plurality of third read access transistors formed in the first NP region.

### Claim 13 (depends on 8)

The apparatus of claim 8, wherein the first memory cell further comprises a plurality of fourth read access transistors formed in the first NP region.

### Claim 14

An apparatus, comprising:
a first memory cell comprising:
a plurality of first write access transistors formed within a first area; and
a plurality of first read access transistors formed within a second area; and
a second memory cell comprising:
a plurality of second write access transistors formed within a third area between the first area and the second area,
wherein the first memory cell and the second memory cell are memory cells in adjacent rows of the same column.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the second memory cell further comprises a plurality of second read access transistors formed within the second area.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the second read access transistors and the second write transistors are formed in the same n-plus (NP) region overlapping the second area and the third area.

### Claim 17 (depends on 15)

The apparatus of claim 15, wherein the second read access transistors are formed in an NP region within the second area, and the second write transistors are formed in a p-plus (PP) region adjacent to the NP region, the PP region overlapping the first area and the third area.

### Claim 18 (depends on 14)

The apparatus of claim 14, wherein the first write access transistors are formed in an NP region and the first read access transistors are formed in another NP region.

### Claim 19 (depends on 14)

The apparatus of claim 14, wherein the first memory cell further comprises third read access transistors formed within a fourth area, the first area being between the third area and the fourth area; and
the second memory cell further comprises fourth read access transistors formed within the fourth area.

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein the third read access transistors and the fourth read access transistors are formed in an NP region overlapping the first area and the fourth area.