# US 11,910,586 B2 · Integrated circuit and static random access memory thereof

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- Number: US 11,910,586 B2
- Document ID: US11910586B2
- Status: Granted
- Kind: B2
- Application number: 17/976,317
- Filed: 2022-10-28
- Published: 2023-03-02
- Granted: 2024-02-20
- Earliest claimed: 2017-10-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jhon-Jhy Liaw
- Web page: https://patentgrep.com/patent/US11910586B2

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- G11C 11/419: Read-write [R-W] circuits
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/517: {characterised by the conducting layers}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0179: {the gate conductors having different shapes or dimensions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 89/10: Integrated device layouts
- H10P 50/264: {by chemical means}
- G11C 11/412: using field-effect transistors only
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/859: {comprising both N-type and P-type wells, e.g. twin-tub}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An IC structure comprises a substrate, a first SRAM cell, and a second SRAM cell. The first SRAM cell is formed over the substrate and comprises a first N-type transistor. The second SRAM cell is formed over the substrate and comprises a second N-type transistor. A gate structure of first N-type transistor of the first SRAM cell has a different work function metal composition than a gate structure of the second N-type transistor of the second SRAM cell.

## Claims

### Claim 1

A device, comprising:
a first transistor formed on a first active region within a first well region;
a second transistor formed on a second active region within a second well region, the second well region forming a PN junction with the first well region; and
a shared gate structure shared by the first transistor and the second transistor, the shared gate structure comprising:
a first work function film overlapping the first active region;
a second work function film overlapping the second active region, the second work function film having a different material composition than the first work function film; and
a conductive film overlapping both the first work function film and the second work function film.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first work function film has a thickness less than a thickness of the second work function film.

### Claim 3 (depends on 1)

The device of claim 1, wherein the second work function film laterally extends from the first work function film.

### Claim 4 (depends on 1)

The device of claim 1, wherein the first work function film and the second work function film form a stepped surface profile, the stepped surface profile has a step rise over the PN junction formed by the first and second well regions.

### Claim 5 (depends on 1)

The device of claim 1, wherein the first work function film is a multilayer stack of a first work function layer and a second work function layer, and the second work function film is a multilayer stack of a third work function layer and a fourth work function layer.

### Claim 6 (depends on 5)

The device of claim 5, wherein the third work function layer laterally extends from the first work function layer, and the third work function layer is thicker than the first work function layer.

### Claim 7 (depends on 6)

The device of claim 6, wherein the fourth work function layer laterally extends from the second work function layer, and a thickness difference between the second and fourth work function layers is smaller than a thickness difference between the first and third work function layers.

### Claim 8 (depends on 1)

The device of claim 1, wherein the first transistor is a pull-down transistor of a first static random access memory (SRAM) cell, and the second transistor is a pull-up transistor of the first SRAM cell.

### Claim 9 (depends on 8)

The device of claim 8, further comprising:
a pull-down transistor of a second SRAM cell, wherein the pull-down transistor of the second SRAM cell has a threshold voltage different than a threshold voltage of the pull-down transistor of the first SRAM cell by at least 40 mV.

### Claim 10 (depends on 8)

The device of claim 8, further comprising:
a pull-up transistor of a second SRAM cell, wherein the pull-up transistor of the second SRAM cell has a threshold voltage different than a threshold voltage of the pull-up transistor of the first SRAM cell by at least 40 mV.

### Claim 11

A device, comprising:
a first active region extending along a first direction within a first well region;
a second active region extending along the first direction within a second well region;
an isolation region between the first active region and the second active region, the isolation region having a bottom surface in contact with a PN junction between the first well region and the second well region; and
a gate structure continuously extending across the first active region and the second active region along a second direction different from the first direction, the gate structure comprising:
a first work function film extending across the first active region;
a second work function film, different from the first work function film, extending across the second active region; and
a metal structure extending across both the first work function film and the second work function film.

### Claim 12 (depends on 11)

The device of claim 11, wherein the first active region is a first fin extending from a substrate.

### Claim 13 (depends on 12)

The device of claim 12, wherein the second active region is a second fin extending parallel with the first fin.

### Claim 14 (depends on 11)

The device of claim 11, wherein the second work function film is thicker than the first work function film.

### Claim 15 (depends on 11)

The device of claim 11, wherein the first work function film is first multilayer stack, the second work function film is a second multilayer stack, and a bottommost layer in the second multilayer stack is thicker than a bottommost layer in the first multilayer stack.

### Claim 16 (depends on 15)

The device of claim 15, wherein a top surface of the bottommost layer in the first multilayer stack and a top surface of the bottommost layer in the second multilayer stack form a stepped profile over the isolation region.

### Claim 17

A device, comprising:
a substrate;
a first SRAM cell formed over the substrate, the first SRAM cell comprising a first N-type transistor having a first gate structure, the first gate structure having a first work function metal layer; and
a second SRAM cell formed over the substrate, the second SRAM cell comprising a second N-type transistor having a second gate structure, the second gate structure having a second work function metal layer,
wherein the first work function metal layer is a stacked film of a first layer and a second layer, the second work function metal layer is a stacked film of a third layer and a fourth layer, the first layer of the first work function metal layer is thicker than the third layer of the second work function metal layer, and the second layer of the first work function metal layer has a thickness substantially the same as a thickness of the fourth layer of the second work function metal layer.

### Claim 18 (depends on 17)

The device of claim 17, wherein a threshold voltage of the first N-type transistor of the first SRAM cell is different than a threshold voltage of the second N-type transistor of the second SRAM cell by at least 40 mV.

### Claim 19 (depends on 17)

The device of claim 17, wherein the first N-type transistor is a pull-down transistor of the first SRAM cell.

### Claim 20 (depends on 17)

The device of claim 17, wherein the second N-type transistor is a pull-down transistor of the second SRAM cell.