# US 11,910,585 B2 · Well pick-up region design for improving memory macro performance

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- Number: US 11,910,585 B2
- Document ID: US11910585B2
- Status: Granted
- Kind: B2
- Application number: 17/873,626
- Filed: 2022-07-26
- Published: 2022-11-10
- Granted: 2024-02-20
- Earliest claimed: 2018-11-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chih-Chuan Yang; Chang-Ta Yang; Ping-Wei Wang
- Web page: https://patentgrep.com/patent/US11910585B2

## CPC

- H10B 10/00: Static random access memory [SRAM] devices
- H10D 89/10: Integrated device layouts
- G06F 30/30: Circuit design
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- G11C 11/412: using field-effect transistors only
- H10B 10/12: {comprising a MOSFET load element}
- H10D 84/0156: {Manufacturing their doped wells}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region, a WPU region, a first well extending lengthwise along a first direction through the circuit region and into the WPU region, a second well extending lengthwise along the first direction through the circuit region and into the WPU region, and a third well physically connecting a portion of the first well in the WPU region and a portion of the second well in the WPU region.

## Claims

### Claim 1

A semiconductor device, comprising:
a circuit region;
a well pick-up (WPU) region;
a first well extending lengthwise along a first direction through the circuit region and into the WPU region;
a second well extending lengthwise along the first direction through the circuit region and into the WPU region; and
a third well physically connecting a portion of the first well in the WPU region and a portion of the second well in the WPU region,
wherein the first well, the third well, and the second well are sequentially arranged along a second direction perpendicular to the first direction.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first, second, and third wells form a continuous well of a same conductivity type.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the same conductivity type is n-type.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
a fourth well extending lengthwise along the first direction, wherein the first well, the fourth well, and the second well are sequentially arranged along the second direction.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the first, second, and third wells are of a first conductivity type, and the fourth well is of a second conductivity type opposite to the first conductivity type.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the first conductivity type is n-type and the second conductivity type is p-type.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein each of the circuit region and the WPU region extends lengthwise along a second direction perpendicular to the first direction.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the WPU region is a first WPU region, the semiconductor device further comprising:
a second WPU region, wherein the first WPU region, the circuit region, and the second WPU region are sequentially arranged along the first direction; and
a fourth well sandwiched between the first well and the second well, wherein the fourth well extending lengthwise along the first direction through the circuit region and into the second WPU region.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the first WPU region and the second WPU region are of a same conductivity type.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, further comprising:
a third WPU region,
wherein:
the first WPU region, the circuit region, the second WPU region, and the third WPU region are sequentially arranged along the first direction,
the first WPU region and the second WPU region are of a first conductivity type,
the third WPU region is of a second conductivity type opposite to the first conductivity type, and
the fourth well extends through the second WPU region and into the third WPU region.

### Claim 11

A memory device, comprising:
a memory cell region;
a first well pick-up (WPU) region;
a second WPU region, wherein the first WPU region, the memory cell region, and the second WPU region are sequentially arranged along a first direction; and
an n-type well disposed on the first WPU region, the memory cell region, and the second WPU region,
wherein the n-type well has a first portion extending continuously from the first WPU region to the second WPU region along the first direction, a second portion disposed on the first WPU region and extending lengthwise along a second direction perpendicular to the first direction, and a third portion disposed on the second WPU region and extending lengthwise along the second direction, wherein the second portion and the third portion are disposed on two sides of the first portion, and wherein the first, second, and third portions are continuously connected.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein each of the first WPU region, the memory cell region, and the second WPU region extends lengthwise in the second direction.

### Claim 13 (depends on 11)

The memory device of claim 11, wherein the first WPU region and the second WPU region are n-type.

### Claim 14 (depends on 11)

The memory device of claim 11, further comprising:
a p-type well in direct contact with the n-type well, wherein the p-type well is disposed at least on the first WPU region and the memory cell region.

### Claim 15 (depends on 14)

The memory device of claim 14, further comprising:
a third WPU region, wherein the third WPU region, the first WPU region, the memory cell region, and the second WPU region are sequentially arranged along the first direction, wherein the first and third WPU regions are of opposite conductivity types, and wherein the p-type well extends lengthwise along the first direction through the first WPU region and into the third WPU region.

### Claim 16 (depends on 11)

The memory device of claim 11, wherein the n-type well has a fourth portion disposed at least on the memory cell region and the first WPU region, the fourth portion extends parallel to the first portion, and the third portion physically connects the first portion and the fourth portion.

### Claim 17

A semiconductor device, comprising:
a circuit region;
a first well-pick up (WPU) region;
a first well oriented lengthwise along a first direction in the circuit region and extending into the first WPU region, the first well having a first conductivity type; and
a second well oriented lengthwise along the first direction in the circuit region and extending into the first WPU region, the second well having a second conductivity type different from the first conductivity type,
wherein a width of the first well in the circuit region is less than a width of the first well in the first WPU region, and wherein the second well surrounds the first well.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, further comprising:
a second WPU region,
wherein the first WPU region is disposed between the circuit region and the second WPU region, and the second well extends further into the second WPU region.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, further comprising:
first contact features disposed over the first well in the first WPU region and arranged in a first number of rows along the first direction; and
second contact features disposed over the second well in the second WPU region and arranged in a second number of rows along the first direction,
wherein the first number of rows is less than the second number of rows.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, further comprising:
a second WPU region,
wherein the circuit region is disposed between the first WPU region and the second WPU region, and the first well extends further into the second WPU region.