# US 11,909,670 B2 · Power throttle for network switches > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,909,670 B2 - Document ID: US11909670B2 - Status: Granted - Kind: B2 - Application number: 17/845,854 - Filed: 2022-06-21 - Published: 2022-10-06 - Granted: 2024-02-20 - Earliest claimed: 2020-07-31 - Assignees: Avago Technologies International Sales Pte. Limited - Applicants: Avago Technologies International Sales Pte. Limited - Inventors: Surendra Anubolu; Sachin Prabhakarrao Kadu; Laxminarasimha Rao Kesiraju; Mohan V. Kalkunte - Web page: https://patentgrep.com/patent/US11909670B2 ## CPC - G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality - H04L 49/505: Corrective measures - G06F 1/3237: by disabling clock generation or distribution - G06F 1/324: by lowering clock frequency - G06F 1/3278: {Power saving in modem or I/O interface} - H04L 49/9084: {Reactions to storage capacity overflow} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract The disclosed systems and methods provide methods and systems for providing power throttling adapted for high performance network switches. A method includes determining, for each of a plurality of measurement periods within a thermal average period, an energy usage estimate for a packet processing block configured to process ingress packets at a power gated clock rate. The method includes determining, for each of the plurality of measurement periods, a target clock rate for the packet processing block based on the determined energy usage estimates to meet a target energy value that is averaged for the thermal average period. The method includes adjusting, for each of the plurality of measurement periods, the power gated clock rate towards the target clock rate, wherein the adjusting causes the packet processing block to process the ingress packets at the adjusted power gated clock rate. ## Claims ### Claim 1 A method comprising: determining, for a time period, an energy usage estimate for packet processing circuitry configured to process one or more packets at a clock rate; determining, for the time period, a target clock rate for the packet processing circuitry based at least in part on the determined energy usage estimate and a target energy value corresponding to the time period; and adjusting, for the time period, the clock rate based at least in part on the target clock rate, wherein the adjusting causes the packet processing circuitry to process the one or more packets at the adjusted clock rate. ### Claim 2 (depends on 1) The method of claim 1, wherein the target clock rate is determined based on a surplus power budget that is credited while the target clock rate exceeds the adjusted clock rate. ### Claim 3 (depends on 2) The method of claim 2, wherein the time period is within a thermal average period and the surplus power budget is reset to zero at a start of the thermal average period. ### Claim 4 (depends on 2) The method of claim 2, wherein the time period is within a thermal average period and the surplus power budget is set to an initial budget value at a start of the thermal average period. ### Claim 5 (depends on 1) The method of claim 1, wherein the target clock rate is determined based on whether a buffer fill rate for the one or more packets exceeds a threshold fill rate. ### Claim 6 (depends on 1) The method of claim 1, wherein the energy usage estimate corresponds to the packet processing circuitry processing a determined number of packet cells from the one or more packets. ### Claim 7 (depends on 1) The method of claim 1, wherein the time period is one of a plurality of time periods within a thermal average period and each of the plurality of time periods comprises a substantially equal time period. ### Claim 8 (depends on 7) The method of claim 7, wherein the adjusting comprises stepwise adjustments of the clock rate using a plurality of adjustment periods after each of the plurality of time periods. ### Claim 9 (depends on 8) The method of claim 8, wherein the plurality of adjustment periods in aggregate comprises a combined time period substantially equal to one of the plurality of time periods. ### Claim 10 (depends on 8) The method of claim 8, wherein each of the plurality of adjustment periods is a time period that is approximately 1 to 10 percent of one of the plurality of time periods. ### Claim 11 (depends on 1) The method of claim 1, wherein the time period is withing a thermal average period that is approximately 100 milliseconds to 10 seconds. ### Claim 12 (depends on 1) The method of claim 1, wherein the time period is one of a plurality of time periods within a thermal average period and each of the plurality of time periods is approximately 1 to 10 percent of the thermal average period. ### Claim 13 (depends on 1) The method of claim 1, wherein the target clock rate is bounded by a predetermined range. ### Claim 14 A system comprising: packet processing circuitry configured to process one or more ingress packets at a clock rate; and processing circuitry configured to: determine, for a time period within a thermal average period, an energy usage estimate for the packet processing circuitry; determine, for the time period, a target clock rate for the packet processing circuitry based at least in part on the determined energy usage estimate to meet a target energy value that is averaged for the thermal average period; and adjust, for the time period, the clock rate based at least in part on the target clock rate, wherein the adjust causes the packet processing circuitry to process the one or more ingress packets at the adjusted clock rate. ### Claim 15 (depends on 14) The system of claim 14, wherein the processing circuitry is further configured to determine the target clock rate based on a surplus power budget that is credited while the target clock rate exceeds the adjusted clock rate, and wherein the surplus power budget is set to one of zero or an initial budget value at a start of the thermal average period. ### Claim 16 (depends on 14) The system of claim 14, wherein the processing circuitry is further configured to determine the target clock rate based on whether a buffer fill rate for the one or more ingress packets exceeds a threshold fill rate. ### Claim 17 (depends on 14) The system of claim 14, wherein the time period is one of a plurality of time periods within the thermal average period and the processing circuitry is further configured to adjust the clock rate using a plurality of adjustment periods after each of the plurality of time periods. ### Claim 18 (depends on 14) The system of claim 14, wherein the time period is within a thermal average period that is approximately 100 milliseconds to 10 seconds. ### Claim 19 (depends on 14) The system of claim 14, wherein the target clock rate is bounded by a predetermined range. ### Claim 20 A non-transitory storage medium comprising instructions that, when executed by one or more processors, cause the processors to perform operations comprising: determining, for each of a plurality of measurement periods within a thermal average period, an energy usage estimate for packet processing circuitry configured to process ingress packets at a clock rate; and adjusting, for each of the plurality of measurement periods, the clock rate based at least in part on the determined energy usage estimates and a target energy value that is averaged for the thermal average period, wherein the adjusting causes the packet processing circuitry to process the ingress packets at the adjusted clock rate.