# US 11,909,416 B2 · Device and method for efficiently encoding quasi-cyclic LDPC codes

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- Number: US 11,909,416 B2
- Document ID: US11909416B2
- Status: Granted
- Kind: B2
- Application number: 18/018,224
- Filed: 2021-07-19
- Published: 2023-07-20
- Granted: 2024-02-20
- Earliest claimed: 2020-07-31
- Assignees: Airbus Defence and Space GmbH
- Applicants: Airbus Defence and Space SAS
- Inventors: Benjamin Gadat; Lyonel Barthe
- Web page: https://patentgrep.com/patent/US11909416B2

## CPC

- H03M 13/116: {Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices}
- H03M 13/1174: {Parity-check or generator matrices built from sub-matrices representing known block codes such as, e.g. Hamming codes, e.g. generalized LDPC codes}
- H03M 13/2906: {using block codes (H03M13/2957 takes precedence)}
- H03M 13/2945: {using at least three error correction codes (H03M13/2957 takes precedence)}
- H03M 13/353: {Adaptation to the channel}
- H03M 13/611: {Specific encoding aspects, e.g. encoding by means of decoding}
- H03M 13/6502: {Reduction of hardware complexity or efficient processing}
- H03M 13/6516: {Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A data encoding device suitable for encoding a plurality of LDPC codes is disclosed including an input interface and an output interface, and a first circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of a first multiplexer circuit, a second circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of the first multiplexer circuit, a third circuit for encoding quasi-cyclic LDPC code, connected at an input to the output of the first multiplexer circuit and at an output to the input of a second multiplexer circuit.

## Claims

### Claim 1

A data encoding device suitable for encoding a plurality of low-density parity-check codes, referred to as LDPC codes, said data encoding device comprising an input interface for receiving data of a data packet to be encoded and an output interface for providing encoded data, said data encoding device comprising:
a first multiplexer circuit and a second multiplexer circuit, said first multiplexer circuit being connected to the input interface and to the input of said second multiplexer circuit, said second multiplexer circuit being connected to the output interface,
a first encoding circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of the first multiplexer circuit,
a second encoding circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of the first multiplexer circuit, said second encoding circuit being arranged in parallel with said first encoding circuit,
a third encoding circuit for encoding quasi-cyclic LDPC code, connected at an input to the output of the first multiplexer circuit and at an output to the input of the second multiplexer circuit.

### Claim 2 (depends on 1)

The data encoding device according to claim 1, comprising at least one memory in which is stored configuration information comprising:
at least one encoding matrix for LDPC code with irregular repetition-accumulation, referred to as LDPC IRA code, for configuring the first encoding circuit,
at least one encoding matrix for LDPC code with simple parity check, referred to as LDPC SPC code, for configuring the second encoding circuit,
at least one encoding matrix for LDPC SPC code, for configuring the third encoding circuit.

### Claim 3 (depends on 2)

The data encoding device according to claim 2, wherein at least one encoding matrix for LDPC code is partially stored, by not storing adjacent rows or columns of said encoding matrix for LDPC code which consist of zero values.

### Claim 4 (depends on 1)

The data encoding device according to claim 1, wherein the third encoding circuit comprises an input buffer of a size suitable for storing data corresponding to at least two data packets to be encoded.

### Claim 5 (depends on 1)

The data encoding device according to claim 1, wherein the first multiplexer circuit is connected to the second multiplexer circuit via a buffer memory.

### Claim 6 (depends on 5)

The data encoding device according to claim 5, wherein the buffer memory between the first multiplexer circuit and the second multiplexer circuit is of a size suitable for storing data corresponding to at least two data packets to be encoded.

### Claim 7 (depends on 1)

The data encoding device according to claim 1, configured to encode LDPC codes whose parity matrix H can be put in the following form:
H
=
(
A
0
D
B
E
0
)
or in the following form:
H
=
(
A
0
D
0
B
E
0
0
C
′
C
″
C
′″
F
)
expressions in which matrices E and F are diagonal matrices, and matrix D is a dual diagonal matrix.

### Claim 8 (depends on 1)

The data encoding device according to claim 1, configured to encode LDPC codes whose parity matrix H can be put in the following form:
H=(A D)
or in the following form:
H
=
(
A
0
D
B
E
0
)
or in the following form:
H
=
(
A
0
D
0
B
E
0
0
C
′
C
″
C
′″
F
)
expressions in which matrices E and F are diagonal matrices, and matrix D is a dual diagonal matrix.

### Claim 9 (depends on 1)

A satellite comprising the data encoding device according to claim 1.

### Claim 10 (depends on 9)

The satellite according to claim 9, wherein the encoded data are transmitted over an optical link.

### Claim 11 (depends on 9)

The satellite according to claim 9, wherein the encoded data are transmitted at a rate greater than 5 Gbit/s.

### Claim 12 (depends on 1)

A method for encoding low-density parity-check codes, referred to as LDPC codes, by means of the data encoding device according to claim 1, comprising:
writing, in parallel, data of a data packet to be encoded, into respective input buffer memories of the first encoding circuit, second encoding circuit, and third encoding circuit,
encoding, in parallel, data in the input buffer memory, by the first encoding circuit and the second encoding circuit,
writing data respectively encoded by the first encoding circuit and/or the second encoding circuit, into the input buffer memory of the third encoding circuit,
encoding the data in the input buffer memory, by the third encoding circuit.

### Claim 13 (depends on 12)

The encoding method according to claim 12, comprising, in parallel with the encoding by the third encoding circuit, a writing, in parallel, of data of another data packet to be encoded, into the respective input buffer memories of the first encoding circuit, second encoding circuit, and third encoding circuit.

### Claim 14 (depends on 12)

The encoding method according to claim 12, wherein, the data encoding device comprising a buffer memory between the first multiplexer circuit and the second multiplexer circuit, the data of the data packet are written into said buffer memory in parallel with the writing into the respective input buffer memories of the first encoding circuit, second encoding circuit, and third encoding circuit.

### Claim 15 (depends on 1)

A configuration program product comprising instructions which, when implemented to configure a programmable logic device, configure said programmable logic device to form the data encoding device according to claim 1.