# US 11,909,415 B2 · Memory system

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- Number: US 11,909,415 B2
- Document ID: US11909415B2
- Status: Granted
- Kind: B2
- Application number: 17/694,057
- Filed: 2022-03-14
- Published: 2023-03-30
- Granted: 2024-02-20
- Earliest claimed: 2021-09-22
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Masahiro Kiyooka; Riki Suzuki; Yoshihisa Kojima
- Web page: https://patentgrep.com/patent/US11909415B2

## CPC

- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- H03M 13/1125: {using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs}
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/3404: {Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells}
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}
- G11C 29/021: {in voltage or current generators}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- H03M 13/098: {using single parity bit}
- H03M 13/1108: {Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping}
- H03M 13/3715: {Adaptation to the number of estimated errors or to the channel state}
- H03M 13/6325: {Error control coding in combination with demodulation}
- G11C 7/04: with means for avoiding disturbances due to temperature effects
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/32: Timing circuits
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- H03M 13/45: Soft decoding, i.e. using symbol reliability information (H03M13/41 takes precedence)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of memory cells. The memory controller is configured to control the nonvolatile memory. In read operation for the memory cells, the memory controller is configured to: perform tracking including a plurality of reads in which a read voltage is shifted; determine a hard bit read voltage based on results of the tracking; calculate a soft bit read voltage based on the determined hard bit read voltage; perform soft bit read using the calculated soft bit read voltage; and perform a soft bit decoding process using a result of the soft bit read and a log-likelihood ratio table associated with the calculated soft bit read voltage.

## Claims

### Claim 1

A memory system, comprising:
a nonvolatile memory including a plurality of memory cells; and
a memory controller configured to control the nonvolatile memory,
wherein in read operation for the memory cells, the memory controller is configured to:
perform tracking including a plurality of reads in which a read voltage is shifted;
determine a hard bit read voltage based on results of the tracking;
calculate a soft bit read voltage based on the determined hard bit read voltage;
perform soft bit read using the calculated soft bit read voltage; and
perform a soft bit decoding process using a result of the soft bit read and a log-likelihood ratio table associated with the calculated soft bit read voltage,
wherein:
the memory controller includes a storage circuit configured to store a first table that stores a set value of the soft bit read voltage and a second table that stores a set limit value of the read voltage; and
the memory controller is configured to:
calculate a difference between the determined hard bit read voltage and a set limit value corresponding to the determined hard bit read voltage in the second table; and
calculate a soft bit read voltage using a reference value corresponding to the difference in the first table.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein when the difference is less than a first threshold value, the memory controller adjusts intervals between soft bit read voltages set between a soft bit read voltage corresponding to the set limit value and the determined hard bit read voltage.

### Claim 3 (depends on 2)

The memory system of claim 2, wherein when the difference is less than the first threshold value, the memory controller adjusts the intervals between soft bit read voltages set between a soft bit read voltage corresponding to the set limit value and the determined hard bit read voltage at equal intervals.

### Claim 4 (depends on 1)

The memory system of claim 1, wherein when the difference is equal to or more than a second threshold value, the memory controller adjusts intervals between soft bit read voltages set between a soft bit read voltage corresponding to the set limit value and the determined hard bit read voltage.

### Claim 5 (depends on 4)

The memory system of claim 4, wherein when the difference is equal to or more than the second threshold value, the memory controller adjusts the intervals between soft bit read voltages set between a soft bit read voltage corresponding to the set limit value and the determined hard bit read voltage at equal intervals.

### Claim 6 (depends on 1)

The memory system of claim 1, wherein:
a threshold voltage distribution of the memory cells includes adjacent first and second states, the second state being higher than the first state; and
the memory controller is configured to:
calculate a first inclination value from a valley portion between the first and second states, based on a result obtained alongside the second state among the results of the tracking; and
adjust intervals between soft bit read voltages set in a negative direction with the determined hard bit read voltage as a reference, based on the first inclination value.

### Claim 7 (depends on 6)

The memory system of claim 6, wherein the memory controller adjusts the intervals between soft bit read voltages set in the negative direction more narrowly as the first inclination value becomes larger.

### Claim 8 (depends on 1)

The memory system of claim 1, wherein:
a threshold voltage distribution of the memory cells includes adjacent first and second states, the second state being higher than the first state; and
the memory controller is configured to:
calculate a second inclination value from a valley portion between the first and second states, based on a result obtained alongside the first state among the results of the tracking; and
adjust intervals between soft bit read voltages set in a positive direction with the determined hard bit read voltage as a reference, based on the second inclination value.

### Claim 9 (depends on 8)

The memory system of claim 8, wherein the memory controller adjusts the intervals between soft bit read voltages set in the positive direction more narrowly as the second inclination value becomes larger.

### Claim 10 (depends on 1)

The memory system of claim 1, wherein:
the memory controller includes a storage circuit which stores a stress information table that stores stress states of the memory cells; and
when the memory controller calculates the soft bit read voltage, the memory controller refers to the stress information table and uses a correction value of the soft bit read voltage based on the stress states of the memory cells.

### Claim 11 (depends on 10)

The memory system of claim 10, wherein the memory controller uses as the stress states at least one of information items of the number of times of writing and erasure, stored time after writing, the number of times of reading, and temperature during writing.

### Claim 12 (depends on 1)

The memory system of claim 1, wherein:
the memory controller configured to include a storage circuit which stores a log-likelihood ratio table set;
the log-likelihood ratio table set includes a plurality of log-likelihood ratio tables;
the log-likelihood ratio tables are each associated with a combination of soft bit read voltages used in the soft bit read and includes log-likelihood ratio information that is optimized for the combination; and
the memory controller uses a log-likelihood ratio table associated with the calculated soft bit read voltage in the soft bit decoding process.

### Claim 13 (depends on 1)

The memory system of claim 1, wherein when the memory controller has failed in decoding in the soft bit decoding process, the memory controller is configured to:
calculate a log-likelihood ratio based on the result of the soft bit read; and
perform a soft bit decoding process using an estimated log-likelihood ratio table with the calculated log-likelihood ratio.

### Claim 14 (depends on 1)

The memory system of claim 1, wherein upon receiving a read request from an external host device, the memory controller is configured to:
transmit a command set including the read request to the nonvolatile memory;
receive data from the nonvolatile memory after transmitting the command set; and
perform the tracking when the memory controller fails in decoding in a hard bit decoding process using the received data.

### Claim 15

A memory system, comprising:
a nonvolatile memory including a plurality of memory cells; and
a memory controller which controls the nonvolatile memory,
wherein in read operation for the memory cells, the memory controller is configured to:
perform tracking including a plurality of reads in which a read voltage is shifted;
calculate a soft bit read voltage from results of the tracking; and
perform a soft bit decoding process using the calculated soft bit read voltage,
wherein when the soft bit read voltage is changed in accordance with limitations of a set limit value of the read voltage, the memory controller adjusts intervals between soft bit read voltages set between the changes soft bit read voltage and a hard bit read voltage determined based on the results of the tracking.

### Claim 16 (depends on 15)

The memory system of claim 15, wherein:
a threshold voltage distribution of the memory cells includes adjacent first and second states, the second state being higher than the first state; and
the memory controller is configured to:
calculate a first inclination value based on data obtained alongside the second state from a valley portion between the first and second states, based on the results of the tracking for the first and second states;
calculate a second inclination value based on data obtained alongside the first state from the valley part; and
calculate a soft bit read voltage based on the first inclination value and the second inclination value.

### Claim 17 (depends on 15)

The memory system of claim 15, wherein:
the memory controller includes a storage circuit configured to store a first table and a second table, the first table storing stress states of the memory cells, the second table storing correction values of soft bit read voltages corresponding to the stress states; and
the memory controller is configured to calculate a soft bit read voltage using the correction values of the soft bit read voltages corresponding to the stress states corresponding to a shape of a threshold voltage distribution estimated based on the results of the tracking.

### Claim 18 (depends on 15)

The memory system of claim 15, wherein when the memory controller has failed in decoding in the soft bit decoding process, the memory controller is configured to:
calculate a log-likelihood ratio based on the result of the soft bit read using the calculated soft bit read voltage; and
perform a soft bit decoding process using an estimated log-likelihood ratio table with the calculated log-likelihood ratio.