# US 11,909,414 B2 · Control of analogue to digital converters > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,909,414 B2 - Document ID: US11909414B2 - Status: Granted - Kind: B2 - Application number: 17/824,108 - Filed: 2022-05-25 - Published: 2022-12-01 - Granted: 2024-02-20 - Earliest claimed: 2021-05-26 - Assignees: Nordic Semiconductor ASA - Applicants: Nordic Semiconductor ASA - Inventors: Henrik Fon; Tor Øyvind Vedal - Web page: https://patentgrep.com/patent/US11909414B2 ## CPC - H03M 1/38: sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) - H03M 1/46: with digital/analogue converter for supplying reference values to converter - H03K 19/1774: {for global signals, e.g. clock, reset} - H03M 1/1245: {Details of sampling arrangements or methods} - H03M 1/125: {Asynchronous, i.e. free-running operation within each conversion cycle} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A circuit portion comprising a clock domain is disclosed. A first clock is arranged to clock components in the clock domain. An analogue to digital converter is clocked by a second clock with a duty cycle. The second clock is derived from the first clock. The analogue to digital converter is arranged to output a feedback signal upon finishing a conversion of a sample, and the feedback signal is arranged to control the duty cycle. ## Claims ### Claim 1 A circuit portion, comprising: a clock domain comprising a first clock arranged to clock components in the clock domain; an analogue to digital converter clocked by a second clock having a duty cycle, the second clock being derived from the first clock; a sampling module arranged to sample an output of the analogue to digital converter, wherein the sampling module is clocked by the second clock; a re-sampling module clocked by the first clock arranged to re-sample the output of the sampling module; and wherein the analogue to digital converter is arranged to output a feedback signal upon finishing an analogue to digital conversion of a sample, said feedback signal being arranged to control the duty cycle. ### Claim 2 (depends on 1) The circuit portion of claim 1, wherein the feedback signal comprises a signal edge which is triggered upon the analogue to digital converter finishing an analogue to digital conversion of a sample. ### Claim 3 (depends on 1) The circuit portion of claim 1, wherein the duty cycle of the second clock is determined by a signal edge of the feedback signal. ### Claim 4 (depends on 1) The circuit portion of claim 1, wherein a first signal edge of the second clock is triggered by a signal edge of the feedback signal and a second signal edge of the second clock is triggered by a signal edge of the first clock. ### Claim 5 (depends on 1) The circuit portion of claim 1, wherein the sampling module comprises a D-type flip flop. ### Claim 6 (depends on 5) The circuit portion of claim 5, comprising a re-sampling module clocked by the first clock arranged to re-sample the output of the sampling module. ### Claim 7 (depends on 1) The circuit portion of claim 1, comprising a re-sampling module clocked by the first clock arranged to re-sample the output of the sampling module. ### Claim 8 (depends on 1) The circuit portion of claim 1, wherein the re-sampling module comprises a D-type flip flop. ### Claim 9 (depends on 1) The circuit portion of claim 1, wherein the analogue to digital converter is a successive approximation register analogue to digital converter. ### Claim 10 (depends on 1) The circuit portion of claim 1, wherein the second clock is arranged to determine when the analogue to digital converter changes from a conversion mode to a sampling mode and wherein controlling the duty cycle of the second clock controls a duration of the sampling mode and a duration of the conversion mode. ### Claim 11 (depends on 1) The circuit portion of claim 1, wherein the analogue to digital converter comprises one or more internal latches, each internal latch being arranged to latch a bit once said bit has been converted. ### Claim 12 (depends on 11) The circuit portion of claim 11, the internal latch(es) being arranged to only reset on a signal edge of the second clock. ### Claim 13 A method of operating a circuit portion, comprising: clocking components in a clock domain with a first clock; clocking an analogue to digital converter with a second clock, the second clock having a duty cycle, the second clock being derived from the first clock; sampling an output of the analogue to digital converter using a sampling module clocked by the second clock; after said sampling, re-sampling an output of the sampling module with a re-sampling module clocked by the first clock; and outputting a feedback signal from the analogue to digital converter, upon finishing an analogue to digital conversion of a sample, to control the duty cycle.