# US 11,909,408 B2 · SerDes module clock network architecture

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- Number: US 11,909,408 B2
- Document ID: US11909408B2
- Status: Granted
- Kind: B2
- Application number: 17/907,099
- Filed: 2021-03-24
- Published: 2023-04-06
- Granted: 2024-02-20
- Earliest claimed: 2020-12-18
- Assignees: Shenzhen Pango Microsystems Co., Ltd
- Applicants: Shenzhen Pango Microsystems Co., Ltd.
- Inventors: Shengwen Xiang; Ying Liu
- Web page: https://patentgrep.com/patent/US11909408B2

## CPC

- H03L 7/16: Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L 7/1974: {for fractional frequency division}
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A SerDes module clock network architecture comprises, a reference clock input port, a plurality of data transmission channels, several user logic interfaces, several frequency division branches and a phase locked loop. The reference lock input port receives an input clock and conveys the input clock to the phase locked loop, the phase locked loop receives the input lock and outputs a PLL output clock signal, the PLL output clock signal is conveyed to the plurality of data transmission channels, and the PLL output clock signal is conveyed to the frequency division branches, and after frequency division, user interface clocks are output and conveyed to the user logic interfaces. When the PLL output clock signal in a SerDes is provided to an internal dedicated channel, several frequency division branches are also divided, and after frequency division, the signal is output to the user logic interfaces for use by an FPGA.

## Claims

### Claim 1

A SerDes module clock network architecture, comprising a reference clock input port, a plurality of data transmission channels, several user logic interfaces, several frequency division branches and a phase locked loop; wherein
the reference clock input port receives an input clock and conveys the input clock to the phase locked loop;
the phase locked loop receives the input clock and outputs a PLL output clock signal;
the PLL output clock signal is conveyed to the plurality of data transmission channels;
the PLL output clock signal is conveyed to the frequency division branches, and after frequency division, user interface clocks are output and conveyed to the user logic interfaces, wherein each of the frequency division branches is associated with a frequency division coefficient, and the frequency division coefficient of each of the frequency division branches is independent; and
the frequency division branches are in one-to-one correspondence with the user logic interfaces.

### Claim 2 (depends on 1)

The SerDes module clock network architecture according to claim 1, wherein the number of frequency division branches is 2 and the number of user logic interfaces is 2.

### Claim 3 (depends on 1)

The SerDes module clock network architecture according to claim 1, wherein the frequency division coefficient is fractional frequency division or integer frequency division.

### Claim 4 (depends on 1)

The SerDes module clock network architecture according to claim 1, wherein the frequency division coefficient can be is configured by parameters.

### Claim 5 (depends on 1)

The SerDes module clock network architecture according to claim 1, wherein the phase locked loop and the plurality of data transmission channels are separate structures.