Method and system of dynamically controlling reset signal of IQ divider
AssigneeSamsung Electronics Co., Ltd.
InventorsPraveen Rathee, Vishnu Kalyanamahadevi Gopalan Jawarlal, Sanjeeb Kumar Ghosh, Avneesh Singh Verma
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Abstract
A system and method to dynamically control a reset signal for an IQ divider are provided. The system includes an IQ divider configured to output a IQ divider output clock; an input configured to receive a reference clock; a failure sensing circuit configured to sense a failure in the IQ divider output clock, the failure sensing circuit including an automatic frequency calibration (AFC) logic; and a control circuit configured to control a reset signal provided to the IQ divider, based on an output of the failure sensing circuit corresponding the failure sensed by the failure sensing circuit.
Claims20
A system comprising:
- an IQ divider configured to output a IQ divider output clock;
- an input configured to receive a reference clock;
- a failure sensing circuit configured to sense a failure in the IQ divider output clock, the failure sensing circuit comprising an automatic frequency calibration (AFC) logic;
- and
- a control circuit configured to control a reset signal provided to the IQ divider, based on an output of the failure sensing circuit corresponding the failure sensed by the failure sensing circuit.
A method of dynamically controlling a reset signal for an IQ divider by a system, the method comprising:
- monitoring an output frequency of the IQ divider with respect to an input reference clock frequency of a reference clock;
- detecting a failure in the IQ divider based on the monitored output frequency of the IQ divider;
- and
- dynamically controlling, the reset signal based on the detected failure.
An apparatus comprising:
- a memory storing one or more instructions;
- and
- a processor for executing one or more instructions stored in the memory;
- wherein the processor is configured to implement:
- an IQ divider configured to output a IQ divider output clock;
- an input configured to receive a reference clock;
- a failure sensing circuit configured to sense a failure in the IQ divider output clock, the failure sensing circuit comprising an automatic frequency calibration (AFC) logic;
- and
- a control circuit configured to control a reset signal provided to the IQ divider, based on an output of the failure sensing circuit corresponding the failure sensed by the failure sensing circuit.
Dependencies are inferred from the claim text.