# US 11,909,403 B2 · Low power apparatus and method to multiply frequency of a clock

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- Number: US 11,909,403 B2
- Document ID: US11909403B2
- Status: Granted
- Kind: B2
- Application number: 16/870,405
- Filed: 2020-05-08
- Published: 2021-11-11
- Granted: 2024-02-20
- Earliest claimed: 2020-05-08
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Kuan-Yueh Shen; Nasser Kurd
- Web page: https://patentgrep.com/patent/US11909403B2

## CPC

- H03L 7/0814: {the phase shifting device being digitally controlled}
- H03K 5/1565: {the output pulses having a constant duty cycle}
- H03L 7/07: using several loops, e.g. for redundant clock signal generation
- H03L 7/0818: {the controlled phase shifter comprising coarse and fine delay or phase-shifting means}
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A multi-feedback circuit that compares a duty cycle corrected reference clock fREF, and controls a number of identical delay lines to generate a new clock with a frequency that is a multiple (e.g., 32×, 4×, etc.) of the frequency of fREF with approximately 50% duty cycle (DC). The new clock is used as a reference clock to a phase locked loop (PLL) or a multiplying delay locked loop (MDLL) resulting in shorter lock times for the PLL/MDLL, higher bandwidth for the PLL/MDLL, lower long-term output clock jitter. The multi-feedback circuit can also be used as a low power clock generator.

## Claims

### Claim 1

An apparatus comprising:
a duty cycle correction (DCC) circuit to receive a first clock having a first frequency to generate an output which is substantially corrected for duty cycle error; and
a multiplier circuitry coupled to the output of the DCC circuit, wherein the multiplier circuitry is to generate a second clock having a second frequency higher than the first frequency, wherein the multiplier circuitry includes:
a delay line to delay the output of the DCC circuit, and to generate a phase shifted signal; and
a comparator to compare the output of the DCC circuit and the phase shifted signal wherein the delay line is a first delay line, the phase shifted signal is a first phase shifted signal, and the multiplier circuitry comprises a second delay line to delay the first phase shifted signal and generate a second phase shifted signal, an inverter to invert the second phase shifted signal, and a phase detector to receive an output of the inverter, and the output of the DCC circuit.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the multiplier circuitry comprises a finite state machine (FSM) to receive UP and Down signals of the phase detector and to generate one or more controls to control delays of the first and second delay lines in accordance with the UP and Down signals.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the comparator is a first comparator, and wherein the multiplier circuitry comprises:
a third delay line to delay an output of the first comparator, and to generate a third phase shifted signal relative to the output of the DCC circuit; and
a second comparator to compare the output of the first comparator and the third phase shifted signal.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the one or more controls to control delay of the third delay line in accordance with the UP and Down signals.

### Claim 5 (depends on 4)

The apparatus of claim 4 comprises a bias generator to generate bias for the first, second and third delay lines.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the first and second delay lines have substantially a same delay.

### Claim 7 (depends on 3)

The apparatus of claim 3, wherein the third delay line has substantially half a delay of the first or second delay lines.

### Claim 8 (depends on 3)

The apparatus of claim 3, wherein the first and second comparators comprise XOR or XNOR gates.

### Claim 9 (depends on 3)

The apparatus of claim 3, wherein the first, second, and third delay lines comprise one or more delay stages, wherein an individual delay stage includes degenerative n-type or p-type devices.

### Claim 10

An apparatus comprising:
a duty cycle correction (DCC) circuit to receive a first clock having a first frequency to generate an output which is corrected for duty cycle error; and
a multiplier circuitry coupled to the output of the DCC circuit, wherein the multiplier circuitry is to generate a second clock having a second frequency higher than the first frequency, wherein the multiplier circuitry is independent of a phase locked loop, and wherein the multiplier circuitry includes:
a first delay line to delay the output of the DCC circuit and generate a substantially 90 degree phase shifted signal,
an XOR gate to compare the output of the DCC circuit and the substantially 90 degree phase shifted signal,
a second delay line to delay the substantially 90 degree phase shifted signal and generate a substantially 180 degree phase shifted signal,
an inverter to invert the substantially 180 degree phase shifted signal; and
a phase frequency detector to receive an output of the inverter, and the output of the DCC circuit.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the multiplier circuitry comprises a finite state machine (FSM) to receive a phase error from the phase frequency detector and to generate one or more bits to control delays of the first and second delay lines in accordance with the phase error.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the XOR gate is a first XOR gate, and wherein the multiplier circuitry comprises:
a third delay line to delay an output of the first XOR gate, and to generate a substantially 135 degree phase shifted signal relative to the output of the DCC circuit; and
a second XOR gate to compare the output of the first XOR gate and the substantially 135 phase shifted signal.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein:
the one or more bits to control delay of the third delay line in accordance with the phase error;
the first and second delay lines have substantially a same delay; and
the third delay line has substantially half a delay of the first or second delay lines.

### Claim 14

A system comprising:
a crystal oscillator to generate a first clock having a first frequency;
a memory;
a processor coupled to the memory; and
a wireless interface to allow the processor to communicate with another device, wherein the processor includes:
a duty cycle correction (DCC) circuit to receive the first clock to generate an output which is corrected for duty cycle error; and
a multiplier circuitry coupled to the output of the DCC circuit, wherein the multiplier circuitry is to generate a second clock having a second frequency higher than the first frequency, wherein the multiplier circuitry includes:
a delay line to delay the output of the DCC circuit, and to generate a phase shifted signal; and
a comparator to compare the output of the DCC circuit and the phase shifted signal, wherein the delay line is a first delay line, the phase shifted signal is a first phase shifted signal, and the multiplier circuitry comprises a second delay line to delay the first phase shifted signal and generate a second phase shifted signal, an inverter to invert the second phase shifted signal, and a phase detector to receive an output of the inverter, and the output of the DCC circuit.

### Claim 15 (depends on 14)

The system of claim 14 comprises a phase locked loop to receive the second clock as a reference clock.