# US 11,909,402 B2 · Semiconductor device including a pulse amplitude modulation driver > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,909,402 B2 - Document ID: US11909402B2 - Status: Granted - Kind: B2 - Application number: 17/847,307 - Filed: 2022-06-23 - Published: 2023-08-24 - Granted: 2024-02-20 - Earliest claimed: 2022-02-22 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Paul Ranucci; Alan Roth - Web page: https://patentgrep.com/patent/US11909402B2 ## CPC - H03K 7/02: Amplitude modulation, i.e. PAM - H03K 17/687: the devices being field-effect transistors - H03K 17/6872: {using complementary field-effect transistors} - H03K 17/6874: {in a symmetrical configuration} - H03K 5/02: by amplifying (H03K5/04 takes precedence) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Devices and methods are described herein for a pulse amplitude modulation (PAM) driver. In one embodiment, the PAM driver includes a first high-speed buffer configured to output a first voltage, a second high-speed buffer configured to output a second voltage, and a plurality of transistors coupled to the first high-speed buffer and the second high-speed buffer. At least one of the first voltage or the second voltage facilitates selective operation of a transistor of the plurality of transistors to output a third voltage. ## Claims ### Claim 1 A semiconductor device comprising: a first high-speed buffer configured to output a first voltage; a first pre-positioning circuit configured to provide the first high-speed buffer a first reference voltage; a second high-speed buffer configured to output a second voltage; a second pre-positioning circuit configured to provide the second high-speed buffer a second reference voltage different from the first reference voltage; and a plurality of transistors coupled to the first high-speed buffer and the second high-speed buffer, wherein at least one of the first voltage or the second voltage facilitates selective operation of a transistor of the plurality of transistors to output a third voltage. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the third voltage is equivalent to either the first voltage or the second voltage for intermediate states of a pulse amplitude modulation (PAM) signal. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the PAM signal is at least one of a 4-level PAM (PAM-4) signal, an 8-level PAM (PAM-8) signal, or a 16-level PAM (PAM-16) signal. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein operation of the plurality of transistors using either the first voltage or the second voltage facilitates flow of the third voltage that is a non-transient voltage. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the plurality of transistors comprises: a first transistor including a first terminal configured to receive the first voltage and a second terminal connecting to an output node outputting the third voltage; a second transistor including a first terminal configured to receive the second voltage and a second terminal connecting to the output node; a third transistor including a first terminal configured to receive a fourth voltage and a second terminal connecting to the output node; and a fourth transistor including a first terminal configured to connect the ground and a second terminal connecting to the output node. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the first voltage is greater than the second voltage. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein: the first pre-positioning circuit providing the first reference voltage to the first high-speed buffer based on a first preposition signal; and the second pre-positioning circuit providing the second reference voltage to the second high-speed buffer based on a second preposition signal. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein at least one of the first pre-positioning circuit or the second pre-positioning circuit comprises at least one of a multiplexer or a logic circuit. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein at least one of the first high-speed buffer or the second high-speed buffer comprises low dropout regulator (LDO). ### Claim 10 (depends on 1) The semiconductor device of claim 1, further comprising a data bus inversion (DBI) circuit coupled to the first high-speed buffer and the second high-speed buffer, the DBI circuit configured to output data indicating an encoding scheme used for each bit of a data word output by the plurality of transistors. ### Claim 11 (depends on 1) The semiconductor device of claim 1, wherein the first pre-positioning circuit or the second pre-positioning circuit comprises a resistor ladder coupled to the first high-speed buffer or the second high-speed buffer, the resistor ladder configured to generate the first reference voltage or the second reference voltage, respectively. ### Claim 12 A method comprising: providing, by a first pre-positioning circuit, a first reference voltage to a first high-speed buffer; providing, by a second pre-positioning circuit, a second reference voltage different from the first reference voltage to a second high-speed buffer; receiving, by a plurality of transistors, a first voltage from the first high-speed buffer or a second voltage from the second high-speed buffer; selectively operating a transistor of the plurality of transistors based on either the first voltage or the second voltage; and outputting a third voltage based on operation of the transistor. ### Claim 13 (depends on 12) The method of claim 12, wherein the third voltage is equivalent to either the first voltage or the second voltage for intermediate states of a pulse amplitude modulation (PAM) signal. ### Claim 14 (depends on 12) The method of claim 12, wherein the PAM signal is at least one of a 4-level PAM (PAM-4) signal, an 8-level PAM (PAM-8) signal, or a 16-level PAM (PAM-16) signal. ### Claim 15 (depends on 12) The method of claim 12, wherein the selectively operating using either the first voltage or the second voltage facilitates flow of the third voltage that is a non-transient voltage. ### Claim 16 (depends on 12) The method of claim 12, wherein the plurality of transistors comprises: a first transistor including a first terminal configured to receive the first voltage and a second terminal connecting to an output node outputting the third voltage; a second transistor including a first terminal configured to receive the second voltage and a second terminal connecting to the output node; a third transistor including a first terminal configured to receive a fourth voltage and a second terminal connecting to the output node; and a fourth transistor including a first terminal configured to connect the ground and a second terminal connecting to the output node, wherein the first voltage is greater than the second voltage. ### Claim 17 (depends on 12) The method of claim 12, wherein the third voltage indicates an encoding scheme used for each bit of a data word output by the plurality of transistors, a data bus inversion (DBI) circuit coupled to the first high-speed buffer and the second high-speed buffer, the DBI circuit configured to output data. ### Claim 18 (depends on 12) The method of claim 12, further comprising generating, by a resistor ladder of the first pre-positioning circuit or the second pre-positioning circuit, the first reference voltage or the second reference voltage, respectively. ### Claim 19 A pulse amplitude modulation (PAM) driver comprising: a first high-speed buffer configured to output a first voltage; a first pre-positioning circuit configured to provide the first high-speed buffer a first reference voltage; a second high-speed buffer configured to output a second voltage; a second pre-positioning circuit configured to provide the second high-speed buffer a second reference voltage different from the first reference voltage; a first transistor coupled to the first high-speed buffer; a second transistor coupled to the second high-speed buffer, wherein at least one of the first voltage or the second voltage facilitates selective operation of a transistor of a plurality of transistors to output a third voltage equivalent to either the first voltage or the second voltage for intermediate states of a PAM signal. ### Claim 20 (depends on 19) The PAM driver of claim 19, wherein operation of the first transistor or the second transistor using either the first voltage or the second voltage facilitates flow of the third voltage that is a non-transient voltage.